AND8001 Datasheet, PDF (6/8 Pages) ON Semiconductor – ODD NUMBER DIVIDE BY COUNTERS WITH 50% OUTPUTS AND SYNCHRONOUS CLOCKS

Clk in
AND8001/D
DQ
A
Q
C
DQ
B
Q
C
DQ
C
Q
C
Divide By 3
50% Out
D
J
Q
E
K
Q
C
Divide By 6
50% Out
CLK
AQ
BQ
CQ
DQ
OUT, EQ
Figure 6.
Notice FF ”A” was chosen as the FF to drive FF ”E” in
order to align the positive edges of the clock, Divide By 3,
and divide by 6. The overall skew of the output could be
better matched if all the same type of FF and gates are used.
We already know the Divide By 3 is lockup immune,
following flow chart Figure 7 shows that the addition of the
J K does not change that situation for the Divide By 6.
110
000
011
100
101
010
001
111
Figure 7. Divide by 6 Flow Chart
The flow shows no lockup, but if one observes that the J
K is a sort of toggle device it is obvious that it can’t lock up
the counter.
The J K may need bigger input AND gates to accomplish
larger divide numbers. As an example, pick a Divide By 12
and use J K type FF’s to do the function.
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