AND8001 Datasheet, PDF (4/8 Pages) ON Semiconductor – ODD NUMBER DIVIDE BY COUNTERS WITH 50% OUTPUTS AND SYNCHRONOUS CLOCKS

AND8001/D
DQ
A
Q
C
Clk _C
C
Clk
AQ
BQ
CQ
DQ
EQ
OUT
DQ
B
Q
C
DQ
C
Q
C
Divide By 9 50% Counter
Figure 4.
DQ
D
Q
C
DQ
E
Q
C
50%
Out
Choosing to use ”C” as the flip flop to delay by a 1/2 clock
cycle is necessary to accomplish the 50% output required
when ”ANDed” with ”E”.
Another Synchronous 50% counter for Divide By 6, 10,
12, 14, 18, etc. can be realized by the additions of a J K FF
and some gates. Other types of FF’s may be used.
http://onsemi.com
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