AND8001 Datasheet, PDF (3/8 Pages) ON Semiconductor – ODD NUMBER DIVIDE BY COUNTERS WITH 50% OUTPUTS AND SYNCHRONOUS CLOCKS

AND8001/D
We need to know that the counter will go into the flow,
shown in chart 2, if it happens to come up in one of the
unused states at powerup or for any other reason. Figure 3
shows the resulting flow chart of the analysis of the Divide
By 3 counter of Figure 2. There is no state that the counter
can begin in that doesn’t lead to the desired flow after one
clock cycle.
010
000
110
101
011
100
111
001
Figure 3.
Observation shows that FF ”C” follows FF ”B” by a half
a clock cycle and will never be able to lockup making the
analysis of the Divide By 3 sufficient to assure the whole
configuration will have no lockup flow. So; only the 1 1 state
of the divide by three needed to be confirmed.
The method is extendible to other odd larger divide by ”N”
numbers by following the same design flow.
a) Design a stable UP or Down divide by ”N” counter
b) Make the Clock input a 50% duty cycle differential
signal
c) Add a FF to follow one of the FF’s in the counter by
1/2 clock cycle
d) OR/AND the shifted FF with the one that is driving it
to obtain the desired 50% output
Example:
Design a 50% Divide By 9
Use ”D” type FF’s, other types may give smaller
component count
Karnaugh maps yield:
Ad = A*B* Bd = A*B + AB*
Cd = ABC* + CB* + A*C Dd = ABC
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