CAT9557 Datasheet, PDF (5/17 Pages) ON Semiconductor – 8-Bit I2C-Bus and SMBus I/O Port

CAT9557
Table 3. RELIABILITY CHARACTERISTICS
Parameter
Symbol
Reference Test Method
Min
ESD Susceptibility
V_ZAP (Note 2)
JEDEC Standard JESD 22
2000
Latch−up
I_LTH (Notes 2, 3)
JEDEC Standard 17
100
2. This parameter is tested initially and after a design or process change that affects the parameter.
3. Latch−up protection is provided for stresses up to 100 mA on address and data pins from −1 V to VDD +1 V.
Units
V
mA
Table 4. D.C. OPERATING CHARACTERISTICS
(V_DD = 2.3 V to 5.5 V; V_SS =0 V; T_A = -40°C to +85 °C; unless otherwise specified.)
Rating
Symbol
Conditions
Min
Typ
Max
Unit
SUPPLIES
Supply voltage
Supply current
LOW−level standby current
V_DD
2.3
−
5.5
V
I_DD
Operating mode; V_DD = 5.5 V; no load;
−
19
f_SCL = 100 kHz
25
mA
I_stbL
Standby mode; V_DD = 5.5 V;
no load; V_I = V_SS; f_SCL = 0 kHz;
I/O = inputs
−
0.25
3
mA
HIGH−level standby current
I_stbH
Standby mode; V_DD = 5.5 V;
no load; V_I = V_DD; f_SCL = 0 kHz;
I/O = inputs
−
0.25
1
mA
Additional standby current
DI_stb
Standby mode; V_DD = 5.5 V; every LED
−
0.8
I/O at V_I = 4.3 V; f_SCL = 0 kHz
1
mA
Power−on reset voltage (Note 4)
V_POR
INPUT SCL, RESET; INPUT/OUTPUT SDA
No load; V_I = V_DD or V_SS
−
1.65
2.1
V
LOW−level input voltage
HIGH−level input voltage
LOW−level output current
Leakage current
Input capacitance (Note 5)
I/Os
V_IL
V_IH
I_OL
V_OL = 0.4 V; V_DD = 2.3 V
I_L
V_I = V_DD or V_SS
C_i
V_I = V_SS
−0.5
−
0.7V_DD
−
3
−
−1
−
−
6
+0.3V_DD
V
V_DD
V
−
mA
+1
mA
10
pF
LOW−level input voltage
V_IL
−0.5
−
HIGH−level input voltage
V_IH
2.0
−
LOW−level output current (Note 6)
I_OL
V_OL = 0.5 V, V_DD = 2.3 V
8
10
HIGH−level output current (Note 7)
I_OH
Except pin I_O0; V_OH = 2.4 V; V_DD = 3 V
−4
−
Pin I_O0; V_OH = 4.6 V
−
−
Input leakage current
I_LI
V_DD = 5.5 V; V_I = V_SS
−
−
Input capacitance (Note 5)
C_i
−
−
Output capacitance (Note 5)
C_o
−
−
SELECT INPUTS A0, A1, A2
+0.8
V
5.5
V
−
mA
−
mA
1
mA
−100
mA
5
pF
5
pF
LOW−level input voltage
V_ILA
−0.5
−
+0.8
V
HIGH−level input voltage
V_IHA
2.0
−
5.5
V
Input leakage current
I_LIA
−1
−
+1
mA
4. V_DD must be lowered to 0.2 V in order to reset part.
5. This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
6. The total amount sunk by all I/Os must be limited to 100 mA and 25 mA per bit.
7. The total current sourced by all I/Os must be limited to 85 mA and 20 mA per bit.
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