CAT9557 Datasheet, PDF (10/17 Pages) ON Semiconductor – 8-Bit I2C-Bus and SMBus I/O Port

CAT9557
Acknowledge
After a successful data transfer, each receiving device is
required to generate an acknowledge. The acknowledging
device pulls down the SDA line during the ninth clock cycle,
signaling that it received the 8 bits of data. The SDA line
remains stable LOW during the HIGH period of the
acknowledge related clock pulse (Figure 9).
The CAT9557 responds with an acknowledge after
receiving a START condition and its slave address. If the
device has been selected along with a write operation, it
responds with an acknowledge after receiving each 8−bit byte.
When the CAT9557 begins a READ mode it transmits 8
bits of data, releases the SDA line, and monitors the line for
an acknowledge. Once it receives this acknowledge, the
CAT9557 will continue to transmit data. If no acknowledge
is sent by the Master, the device terminates data transmission
and waits for a STOP condition. The master must then issue
a STOP condition to return the CAT9557 to the standby
power mode and place the device in a known state.
Registers and Bus Transactions
Refer to Figure 2. Block Diagram of CAT9557.
The CAT9557 consists of an input port register, an output
port register, a polarity inversion register and a
configuration register. Table 7 shows the register address
table. Tables 8 to 11 list Register 0 through Register 3
information.
Table 7. REGISTER COMMAND BYTE
Command
(hex)
Protocol
Function
0x00
Read byte
Input port register
0x01
Read/write byte
Output port register
0x02
Read/write byte Polarity inversion register
0x03
Read/write byte
Configuration register
The command byte is the first byte to follow the device
address byte during a write/read bus transaction. The
register command byte acts as a pointer to determine which
register will be written or read.
The input port register is a read only port. It reflects the
incoming logic levels of the I/O pins, regardless of whether
the pin is defined as an input or an output by the
configuration register. Writes to the input port register are
ignored. The default value, X, is determined by the
externally applied logic level.
Table 8. REGISTER 0 −
Input Port Register Bit Allocation
Bit
76543210
Symbol I7 I6 I5 I4 I3 I2 I1 I0
Default x x x x x x x x
Table 9. REGISTER 1 −
Output Port Register Bit Allocation
Bit
76543210
Symbol O7 O6 O5 O4 O3 O2 O1 O0
Default 0 0 0 0 0 0 0 0
Table 10. REGISTER 2 −
Polarity Inversion Register Bit Allocation
Bit
76543210
Symbol N7 N6 N5 N4 N3 N2 N1 N0
Default 1 1 1 1 0 0 0 0
Table 11. REGISTER 3 −
Configuration Register Bit Allocation
Bit
76543210
Symbol C7 C6 C5 C4 C3 C2 C1 C0
Default 1 1 1 1 1 1 1 1
The output port register sets the outgoing logic levels of
the I/O ports, defined as outputs by the configuration
register. Bit values in this register have no effect on I/O pins
defined as inputs. Reads from the output port register reflect
the value that is in the flip−flop controlling the output, not
the actual I/O pin value.
The polarity inversion register allows the user to invert the
polarity of the input port register data. If a bit in this register
is set (“1”) the corresponding input port data is inverted. If
a bit in the polarity inversion register is cleared (“0”), the
original input port polarity is retained.
The configuration register sets the directions of the ports.
Set the bit to “1” in the configuration register to enable the
corresponding port pin as an input with a high impedance
output driver. If a bit in this register is cleared (“0”), the
corresponding port pin is enabled as an output. At
power−up, the I/Os are configured as inputs.
Data is transmitted to the CAT9557 registers using the
write mode shown in Figure 11 and Figure 12.
The CAT9557 registers are read according to the timing
diagrams shown in Figure 13 and Figure 14. Once a
command byte has been sent, the register which was
addressed will continue to be accessed by reads until a new
command byte will be sent.
Power−On Reset Operation
When power is applied to V_DD, an internal Power−On
Reset (POR) holds the CAT9557 in a reset condition until
V_DD has reached VPOR. At that point, the reset condition is
released and the CAT9557 registers and I²C−bus/SMBus
state machine will initialize to their default states.
Thereafter, V_DD must be lowered below 0.2 V to reset the
device.
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