CAT9557 Datasheet, PDF (11/17 Pages) ON Semiconductor – 8-Bit I2C-Bus and SMBus I/O Port

CAT9557
SCL 1 2 3 4 5 6 7 8 9
slave address
command byte
SDA S 0 0 1 1 A2 A1 A0 0 A 0 0 0 0 0 0 0 1 A
data to port
DATA 1
STOP
condition
AP
START condition
write to port
data out from port
R/W acknowledge
from slave
acknowledge
from slave
Figure 11. Write to Output Port Register
acknowledge
from slave
t_v(Q)
DATA 1
VALID
SCL 1 2 3 4 5 6 7 8 9
slave address
command byte
SDA S 0 0 1 1 A2 A1 A0 0 A 0 0 0 0 0 0 1 1/0 A
data to register
DATA
START condition
R/W acknowledge
from slave
acknowledge
from slave
Figure 12. Write to I/O Configuration or Polarity Inversion Registers
STOP
condition
AP
acknowledge
from slave
slave address
SDA S 0 0 1 1 A2 A1 A0 0 A
command byte
A ^(cont.)
START condition
R/W
acknowledge
from slave
slave address
acknowledge
from slave
data from register
data from register
(cont.) _{S 0 0 1 1 A2 A1 A0 1 A}
DATA (first byte)
A
DATA (last byte)
NA P
(repeated)
START condition
R/W
acknowledge
from slave
acknowledge
from master
no acknowledge
from master _STOP
condition
at this moment master−transmitter becomes master−receiver
and slave−receiver becomes slave−transmitter
Figure 13. Read from Register
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