LC75886PW Datasheet, PDF (4/36 Pages) ON Semiconductor – 1/4 and 1/3-Duty LCD Display Driver

1. When CL is stopped at the low level
LC75886PW
CE
VIH1
CL 50%
VIL1
tr
DI ^VIH1
VIL1
t_φH
t_φL
tf
tds
tdh
DO
2. When CL is stopped at the high level
VIH1
tcp tcs
tdc
D0
D1
[Figure 2]
VIL1
tch
tdr
CE
CL
tf
DI
DO
VIH1
t_φL
t_φH
VIH1
50%
VIL1
tr
tcp tcs
VIH1
VIL1
tds
tdh
D0
D1
tdc
[Figure 3]
3. OSC pin clock timing in external clock operating mode
OSC
tCKH
tCKL
VIH3
50%
VIL3
[Figure 4]
1
fCK= _tCKH+tCKL [kHz]
DCK=
tCKH
tCKH + tCKL
×100[%]
VIL1
tch
tdr
No.A1391-4/36