LC75886PW Datasheet, PDF (25/36 Pages) ON Semiconductor – 1/4 and 1/3-Duty LCD Display Driver

LC75886PW
3. Pin states during the reset period
Pin
State during reset
S1/P1 to S4/P4
L *5
S5 to S53
L
COM1 to COM3
L
COM4/S54
L *6
KS1/S55, KS2/S56
L *5
KS3 to KS6
L *7
P5/S57
L *8
OSC
Z *9
DO
H *10
Note: *5. These output pins are forcibly set to the segment output function and held low.
*6. This output pin is forcibly set to the common output function and held low.
*7. These output pins are forcibly held fixed at the low level.
*8. This output pin is forcibly set to the general-purpose output port function and held low.
*9. This I/O pin is forcibly set to the high-impedance state.
*10.Since this output pin is an open-drain output, a pull-up resistor of between 1 and 10kΩ is required. This pin
remains high during the reset period even if a key data read operation is performed.
Notes on the OSC Pin Peripheral Circuit
1. RC oscillator operationg mode (Control data bit OC=0)
When RC oscillator operationg mode is selected, an external resistor ROSC and an external capacitor COSC must be
connected between the OSC pin and GND.
ROSC
OSC
COSC
2. External clock operating mode (Control data bit OC=1 )
When selecting the external clock operating mode, connect a current protection resistor Rg (4.7 to 47kΩ) between the
OSC pin and the external clock output pin (external oscillator). Determine the value of the resistance according to the
maximum allowable current value of the external clock output pin. Also make sure that the waveform of the external
clock is not excessively distorted.
External clock output pin
External oscillator
OSC
Rg
Note: Allowable current value at external clock output pin > ^VDD
Rg
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