LC75886PW Datasheet, PDF (22/36 Pages) ON Semiconductor – 1/4 and 1/3-Duty LCD Display Driver

Clock Signal Output Waveform
Control data
PC50
PC51
0
1
LC75886PW
The state of P5/S57 output pin
Clock output port (P5) (Clock frequency is fOSC/2 or fCK/2)
P5
1
Tc/2
Tc= _fc
Tc
Voltage Detection Type Reset Circuit (VDET)
This circuit generates an output signal and resets the system when power is first applied and when the voltage drops, i.e.,
when the power supply voltage is less than or equal to the power down detection voltage VDET, which is 2.3V, typical.
To assure that this function operates reliably, a capacitor must be added to the power supply line so that the power
supply voltage VDD rise time when the power is first applied and the power supply voltage VDD fall time when the
voltage drops are both at least 1ms. (See Figure 5 and Figure 6.)
System Reset
The LC75886PW supports the reset methods described below. When a system reset is applied, display is turned off, key
scanning is stopped, all the key data is reset to low, and the general-purpose output ports are fixed at the low level (The
S1/P1 to S4/P4 pins are forcibly set to the segment output port function and fixed at the low level. The P5/S57 pin is
forcibly set to the general-purpose output port function and fixed at the low level). When the reset is cleared, display is
turned on, key scanning is enabled and the general-purpose output ports state setting is enabled.
1. Reset methods
(1) Reset method by the voltage detection type reset circuit (VDET)
If at least 1ms is assured as the supply voltage VDD rise time when power is applied, a system reset will be applied
by the VDET output signal when the supply voltage is brought up. If at least 1 ms is assured as the supply voltage
VDD fall time when power drops, a system reset will be applied in the same manner by the VDET output signal
when the supply voltage is lowered. Note that the reset is cleared at the point when all the serial data (1/4 duty: the
display data D1 to D224 and the control data, 1/3 duty: the display data D1 to D171 and the control data) has been
transferred, i.e., on the fall of the CE signal on the transfer of the last direction data, after all the direction data has
been transferred. (See Figure 5 and Figure 6.)
• 1/4 duty
t1
t2
VDD
CE
D1 to D56
Internal data OC, PC50, PC51, KSC,
S0, S1, K0, K1, P0 to P2, SC
Internal data (D57 to D112, FC0 to FC2)
VDET
Display and control data transfer
Undefined
Undefined
VIL1
Defined
VDET
Undefined
Defined
Undefined
Internal data (D113 to D168)
Undefined
Defined
Undefined
Internal data (D169 to D224)
Undefined
System reset period
Defined
Undefined
Note: t1≥1 [ms](Power supply voltage VDD rise time)
t2≥1 [ms](Power supply voltage VDD fall time)
[Figure 5]
No.A1391-22/36