LC75886PW Datasheet, PDF (2/36 Pages) ON Semiconductor – 1/4 and 1/3-Duty LCD Display Driver

LC75886PW
Specifications
Absolute Maximum Ratings at Ta = 25°C, VSS = 0V
Parameter
Maximum supply voltage
Input voltage
Output voltage
Output current
Allowable power dissipation
Operating temperature
Storage temperature
Symbol
VDD max
VIN1
VIN2
VOUT1
VOUT2
IOUT1
IOUT2
IOUT3
IOUT4
Pd max
Topr
Tstg
Conditions
VDD
CE, CL, DI, RES
OSC, TEST, VDD1, VDD2, KI1 to KI5
DO
OSC, S1 to S57, COM1 to COM4, KS1 to KS6, P1 to P5
S1 to S57
COM1 to COM4
KS1 to KS6
P1 to P5
Ta=85°C
Ratings
Unit
-0.3 to +7.0
V
-0.3 to +7.0
V
-0.3 to VDD+0.3
-0.3 to +7.0
V
-0.3 to VDD+0.3
300
μA
3
1 mA
5
200 mW
-40 to +85
°C
-55 to +125
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
Allowable Operating Ranges at Ta = -40 to +85°C, VSS = 0V
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
Supply voltage
VDD
VDD
4.5
6.0
V
Input voltage
Input high level voltage
VDD1
VDD2
VIH1
VDD1
VDD2
CE, CL, DI, RES
0.4VDD
2/3VDD
1/3VDD
VDD
V
VDD
6.0
VIH2
KI1 to KI5
0.6VDD
VDD
V
Input low level voltage
VIH3
VIL1
OSC: External clock operating mode
CE, CL, DI, RES
0.4VDD
0
VDD
0.2VDD
VIL2
KI1 to KI5
0
0.2VDD
V
VIL3
OSC: External clock operating mode
0
0.2VDD
Recommended external
resistor for RC oscillation
ROSC
OSC: RC oscillation operating mode
39
kΩ
Recommended external
capacitor for RC oscillation
COSC
OSC: RC oscillation operating mode
1000
pF
Guaranteed range of RC oscillation fOSC
OSC: RC oscillation operating mode
19
38
76 kHz
External clock operating frequency
fCK
OSC: External clock operating mode
[Figure4]
10
38
76 kHz
External clock duty cycle
DCK
OSC: External clock operating mode
[Figure4]
30
50
70
%
Data setup time
tds
CL, DI
[Figure2], [Figure3]
160
ns
Data hold time
tdh
CL, DI
[Figure2], [Figure3]
160
ns
CE wait time
tcp
CE, CL
[Figure2], [Figure3]
160
ns
CE setup time
tcs
CE, CL
[Figure2], [Figure3]
160
ns
CE hold time
tch
CE, CL
[Figure2], [Figure3]
160
ns
High level clock pulse width
t_φH
CL
[Figure2], [Figure3]
160
ns
Low level clock pulse width
t_φL
CL
[Figure2], [Figure3]
160
ns
Rise time
tr
CE, CL, DI
[Figure2], [Figure3]
160
ns
Fall time
tf
CE, CL, DI
[Figure2], [Figure3]
160
ns
DO output deley time
tdc
DO RPU=4.7kΩ CL=10pF *1
[Figure2], [Figure3]
1.5
μs
DO rise time
tdr
DO RPU=4.7kΩ CL=10pF *1
[Figure2], [Figure3]
1.5
μs
Note: *1 Since the DO pin is an open-drain output, these times depend on the values of the pull-up resistor
RPU and the load capacitance CL.
No.A1391-2/36