LC75886PW Datasheet, PDF (23/36 Pages) ON Semiconductor – 1/4 and 1/3-Duty LCD Display Driver

• 1/3 duty
VDD
CE
D1 to D57
Internal data OC, PC50, PC51, KSC,
S0, S1, K0, K1, P0 to P2, SC
Internal data (D58 to D114, FC0 to FC2)
Internal data (D115 to D171)
LC75886PW
t1
t2
VDET
Display and control data transfer
Undefined
VIL1
Defined
VDET
Undefined
Undefined
Defined
Undefined
Undefined
System reset period
Defined
Undefined
Note: t1≥1 [ms](Power supply voltage VDD rise time)
t2≥1 [ms](Power supply voltage VDD fall time)
[Figure 6]
(2) Reset method by the RES pin
When power is applied, a system reset is applied by setting the RES pin low level. The reset is cleared by setting the
RES pin high level after all the serial data (1/4 duty: the display data D1 to D224 and the control data, 1/3 duty: the
display data D1 to D171 and the control data) has been transferred.
In the allowable operating range (VDD=4.5 to 6.0V), A reset is applied by setting the RES pin low level.
and the reset is cleared by setting the RES pin high level
2. Internal block states during the reset period
• CLOCK GENERATOR
A reset is applied and either the OSC pin oscillator is stopped or external clock reception is stopped
• COMMON DRIVER, SEGMENT DRIVER & LATCH
A reset is applied and the display is turned off. However, display data can be input to the latch circuit in this state.
• KEY SCAN
A reset is applied, the circuit is set to the initial state, and at the same time the key scan operation is disabled.
• KEY BUFFER
A reset is applied and all the key data is set to low.
• GENERAL PURPOSE PORT
A reset is applied, the circuit is set to the initial state.
• CCB INTERFACE, SHIFT REGISTER, CONTROL REGISTER
Since serial data transfer is possible, these circuits are not reset.
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