82V3001A Datasheet, PDF (4/28 Pages) Integrated Device Technology – WAN PLL WITH SINGLE REFERENCE INPUT

LIST OF FIGURES
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Block Diagram .................................................................................................................................................. 2
IDT82V3001A SSOP56 Package Pin Assignment........................................................................................... 6
State Control Block......................................................................................................................................... 10
State Control Diagram.................................................................................................................................... 11
TIE Control Circuit Diagram ........................................................................................................................... 12
State Switch with TIE Control Block Enabled................................................................................................. 13
State Switch with TIE Control Block Disabled ................................................................................................ 13
DPLL Block Diagram ...................................................................................................................................... 14
Clock Oscillator Circuit ................................................................................................................................... 15
Power-Up Reset Circuit.................................................................................................................................. 15
IDT82V3001A Power Decoupling Scheme .................................................................................................... 16
Input to Output Timing (Normal Mode)........................................................................................................... 25
Output Timing 1.............................................................................................................................................. 26
Output Timing 2.............................................................................................................................................. 27
Input Control Setup and Hold Timing ............................................................................................................. 27
List of Figures
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November 14, 2012