82V3001A Datasheet, PDF (11/28 Pages) Integrated Device Technology – WAN PLL WITH SINGLE REFERENCE INPUT

IDT82V3001A
WAN PLL WITH SINGLE REFERENCE INPUT
Reset *
S0
Freerun
Mode_sel1=1
Mode_sel0=0
AutoTIE _Disable
(Valid Input Reference Signal)
TIE Enable (TIE_en = H)
S1
Normal
Mode_sel1=0
Mode_sel0=0
(Valid Input Reference Signal)
TIE Disable (TIE_en = L)
(Invalid Input Reference Signal)
TIE
Disable
TIE _Enable
(TIE_en _{= L)}
AutoTIE
(TIE_en _{= H)}
Disable
Auto TIE Disable
S3
Holdover
Mode_sel1=0
Mode_sel0=1
Auto ^{TIE Disable}
S2
Auto - Holdover
Mode_sel1=0
Mode_sel0=0
* Note: After reset, Mode_sel1 and Mode_sel0 should be initially set to '10' or '00'.
Figure - 4 State Control Diagram
3.1.1
NORMAL MODE
Normal Mode is typically used when a slave clock source
synchronized to the network is required.
In this mode, the IDT82V3001A provides timing (C1.5o, C3o, C2o,
C4o, C6o, C8o, C16o and C32o) and synchronization (F0o, F8o, F16o,
F32o, TSP, RSP) signals, which are synchronous to the input reference.
The input reference signal has a nominal frequency of 8 kHz, 2.048 MHz
or 1.544 MHz.
From a reset condition, the IDT82V3001A will take 30 seconds at
most to make the output signals synchronous (phase locked) to the input
reference.
Whenever the IDT82V3001A enters Normal Mode, it will give an
indication by setting the NORMAL pin to high.
3.1.2
FAST LOCK MODE
Fast Lock Mode is a submode of Normal Mode. It is used to allow the
IDT82V3001A to lock to a reference more quickly than Normal Mode will
do. Typically, the DPLL will lock to the input reference within 500 ms if
the FLOCK pin is high.
3.1.3
HOLDOVER MODE
Holdover Mode is typically used for short duration (e.g., 2 seconds)
while network synchronization is temporarily disrupted.
In Holdover Mode, the IDT82V3001A provides timing and
synchronization signals, which are not locked to the external reference
signal but based on storage techniques. The storage value is
determined while the device is in Normal Mode and locked to the
external reference signal.
In Normal Mode, when the output signal is locked to the input
reference signal, a numerical value corresponding to the output
frequency is stored alternately in two memory locations every 30 ms.
When the device is switched into Holdover Mode, the stored value in
memory from between 30 ms and 60 ms is used to set the output
frequency of the device.
The frequency accuracy in Holdover Mode is ±0.025 ppm, which
corresponds to the worst case of 18 frame (125 µs per frame) slips in 24
hours. This meets AT&T TR62411 requirement of ±0.37 ppm (255 frame
slips per 24 hours).
The HOLDOVER pin will be set to logic high whenever the
IDT82V3001A goes into Holdover Mode.
FUNCTIONAL DESCRIPTION
11
November 14, 2012