82V3001A Datasheet, PDF (14/28 Pages) Integrated Device Technology – WAN PLL WITH SINGLE REFERENCE INPUT

IDT82V3001A
3.5
DPLL BLOCK
As shown in Figure - 8, the DPLL Block consists of a Phase Detector,
a Limiter, a Loop Filter, a Digital Control Oscillator and Dividers.
WAN PLL WITH SINGLE REFERENCE INPUT
Fraction_T1
Fraction_C6
Output Interface
24.704 MHz
T1_Divider
32.768 MHz
E1_Divider
25.248 MHz
C6_Divider
C1.5o
C3o
C2o
C4o
C8o
C16o
C32o
F0o
F8o
F16o
F32o
RSP
TSP
C6o
Loop Filter
Limiter
Phase
Detector
Feedback
Signal
Frequency
Selection
Circuit
FLOCK
Virtual Reference F_sel1 F_sel0
Figure - 8 DPLL Block Diagram
3.5.1
PHASE DETECTOR (PHD)
In Normal Mode, the Phase Detector compares the virtual reference
signal from the TIE Control Circuit with the feedback signal from the
Frequency Select Circuit, and outputs an error signal corresponding to
the phase difference between the two. This error signal is then sent to
the Limiter circuit for phase slope control.
The feedback signal can be 8 kHz, 2.048 MHz or 1.544 MHz, as
selected by F_sel1 and F_sel0 pins. Refer to Table - 3 for details.
In Freerun or Holdover Mode, the Frequency Select Circuit, the
Phase Detector and the Limiter are not active and the input reference
signal is not used.
3.5.2
LIMITER
The Limiter is used to ensure that the DPLL responds to all input
transient conditions with a maximum output phase slope of 5 ns per 125
µs. This well meets AT&T TR62411 and Telcordia GR-1244-CORE
specifications, which specify the maximum phase slope of 7.6 ns per
125 µs and 81 ns per 1.326 ms respectively.
In Normal Mode, the Limiter receives the error signal from the Phase
Detector, limits the phase slope within 5 ns per 125 µs and sends the
limited signal to the Loop Filter.
The fast lock mode is a submode of Normal Mode. By setting the
FLOCK pin to high, the device will enter fast lock mode. In this mode,
the Limiter is disabled and the DPLL will lock to the incoming reference
within 500 ms.
3.5.3
LOOP FILTER
The Loop Filter ensures that the jitter transfer meets ETS 300 011
and AT&T TR62411 requirements. This Loop Filter works similarly to a
first order low pass filter with 2.1 Hz cutoff frequency for the three valid
input reference signals (8 kHz, 2.048 MHz or 1.544 MHz).
The output of the Loop Filter goes to the Digital Control Oscillator
directly or via the Fraction blocks, in which E1, T1 and C6 signals are
generated.
FUNCTIONAL DESCRIPTION
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November 14, 2012