82V3001A Datasheet, PDF (13/28 Pages) Integrated Device Technology – WAN PLL WITH SINGLE REFERENCE INPUT

IDT82V3001A
WAN PLL WITH SINGLE REFERENCE INPUT
Previous Fref
Current Fref
Time = 0.00 s
Time = 0.25 s
Time = 0.50 s
Time = 0.75 s
Time = 1.0 s
Time = 1.25 s
Time = 1.50 s
Time = 1.75 s
Input Clock
Output Clock
Figure - 6 State Switch with TIE Control Block Enabled
The phase difference in the Storage Circuit can be cleared by
applying a logic low pulse to the TCLR pin. The reset pulse should be at
least 300 ns.
When the IDT82V3001A primarily enters Holdover Mode for short
time periods and then turns back to Normal Mode, the TIE Control
Circuit should not be enabled. This will prevent undesired accumulated
phase change between the input and output.
If the TIE Control Block is disabled manually or automatically during
state switching, the phase of the output signal will align with that of the
new reference. The phase slope limited to 5 ns per 125 µs. Figure - 7
shows the phase transient resulting from a state switch with the TIE
Control Block disabled.
Previous Fref
Current Fref
Time = 0.00 s
Time = 0.25 s
Time = 0.50 s
Time = 0.75 s
Time = 1.0 s
Time = 1.25 s
Time = 1.50 s
Time = 1.75 s
Input Clock
Output Clock
Figure - 7 State Switch with TIE Control Block Disabled
FUNCTIONAL DESCRIPTION
13
November 14, 2012