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LC88FC2F0B Datasheet, PDF (31/47 Pages) ON Semiconductor – 16-bit Microcontroller 384K-byte Flash ROM / 24Kbyte RAM / 100-pin
LC88FC2F0B
Parameter
Symbol
tSU;STO
Applicable
Pin/Remarks
Conditions
SM1CK (PB4)  See Fig. 8.
SM1DA (PB5)
VDD [V]
Specification
Min
typ max Unit
1.0
Tfilt
Stop condition
setup time
Data hold time
Data setup time
tSU;STOx
tHD;DAT
SM1CK (PB4)  Standard clock mode
SM1DA (PB5)
 Specified as interval up to
time when output state starts
2.7 to 3.6
changing.
 High-speed clock mode
 Specified as interval up to
time when output state starts
changing.
SM1CK (PB4)  See Fig. 8.
SM1DA (PB5)
tHD;DATx SM1CK (PB4)  Specified as interval up to 2.7 to 3.6
SM1DA (PB5) time when output state starts
changing.
tSU;DAT SM1CK (PB4)  See Fig. 8.
SM1DA (PB5)
tSU;DATx
SM1CK (PB4)  Specified as interval up to
SM1DA (PB5) time when output state starts
changing.
2.7 to 3.6
tF
SM1CK (PB4)  See Fig. 8.
SM1DA (PB5)
2.7 to 3.6
4.9
1.1
0
1
1
1tSCL-
1.5Tfilt
s
Tfilt
1.5
Tfilt
300
SM0CK and
tF
SM0DA pins fall
time
SM1CK (PB4)  When SMIIC register
SM1DA (PB5) control bits
PSLW=1, PHV=1
3
20+0.1Cb
250
ns
 SM0CK, SM0DA port
output FAST mode
3 to 3.6
100
 Cb  400pF
Note 4-10-1: These specifications are theoretical values. Add margin depending on its use.
Note 4-10-2: The value of Tfilt is determined by the values of the register SMIC1BRG, bits 7 and 6 (BRP1,
BRP0) and the system clock frequency.
BRP1
0
0
1
1
BRP0
0
1
0
1
Tfilt
tCYC1
tCYC2
tCYC3
tCYC4
Set bits (BPR1, BPR0) so that the value of Tfilt falls between the following range:
250 ns ≥ Tfilt > 140 ns
Note 4-10-3: Cb represents the total loads (in pF) connected to the bus pins. Cb  400 pF
Note 4-10-4: The standard clock mode refers to a mode that is entered by configuring SMIC0BRG as follows:
250 ns ≥ Tfilt > 140 ns
BRDQ (bit5) = 1
SCL frequency setting  100 kHz
The high-speed clock mode refers to a mode that is entered by configuring SMIC1BRG as follows:
250 ns ≥ Tfilt > 140 ns
BRDQ (bit5) = 0
SCL frequency setting  400 kHz
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