DAC1208D750 Datasheet, PDF (98/98 Pages) NXP Semiconductors – Dual 12-bit DAC; up to 750 Msps; 2×, 4× or 8× interpolating with JESD204A interface

NXP Semiconductors
DAC1208D750
2×, 4× or 8× interpolating DAC with JESD204A
17. Contents
1
General description . . . . . . . . . . . . . . . . . . . . . . 1
2
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
4
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
5
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
6
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
6.1
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
6.2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
7
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6
8
Thermal characteristics . . . . . . . . . . . . . . . . . . 6
9
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 7
10
Application information. . . . . . . . . . . . . . . . . . 11
10.1
10.2
10.2.1
10.2.2
10.2.3
10.2.4
10.2.5
10.2.5.1
10.2.5.2
10.2.5.3
10.2.5.4
10.2.6
10.3
10.3.1
10.3.2
10.4
10.5
10.6
10.6.1
10.6.2
10.6.3
10.7
10.8
10.9
10.9.1
10.9.1.1
10.9.2
10.10
10.11
10.12
10.13
10.13.1
General description . . . . . . . . . . . . . . . . . . . . 11
JESD204A receiver . . . . . . . . . . . . . . . . . . . . 12
Lane input . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Sync and word align . . . . . . . . . . . . . . . . . . . . 13
Comma detection and word align . . . . . . . . . . 14
Descrambler . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Inter-lane alignment . . . . . . . . . . . . . . . . . . . . 15
Single device operation . . . . . . . . . . . . . . . . . 15
Multi-device operation . . . . . . . . . . . . . . . . . . 15
Master/slave mode . . . . . . . . . . . . . . . . . . . . . 17
All slave mode . . . . . . . . . . . . . . . . . . . . . . . . 20
Frame assembly . . . . . . . . . . . . . . . . . . . . . . . 21
Serial Peripheral Interface (SPI) . . . . . . . . . . . 23
Protocol description . . . . . . . . . . . . . . . . . . . . 23
SPI timing description . . . . . . . . . . . . . . . . . . . 24
Clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
FIR filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Quadrature modulator and Numerically
Controlled Oscillator (NCO) . . . . . . . . . . . . . . 27
NCO in 32-bit . . . . . . . . . . . . . . . . . . . . . . . . . 27
Low-power NCO . . . . . . . . . . . . . . . . . . . . . . . 27
Minus_3dB . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
x / (sin x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
DAC transfer function . . . . . . . . . . . . . . . . . . . 28
Full-scale current . . . . . . . . . . . . . . . . . . . . . . 29
Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
External regulation . . . . . . . . . . . . . . . . . . . . . 29
Full-scale current adjustment . . . . . . . . . . . . . 29
Digital offset correction . . . . . . . . . . . . . . . . . . 30
Analog output . . . . . . . . . . . . . . . . . . . . . . . . . 31
Auxiliary DACs . . . . . . . . . . . . . . . . . . . . . . . . 32
Output configuration . . . . . . . . . . . . . . . . . . . . 33
Basic output configuration . . . . . . . . . . . . . . . 33
10.13.2 DC interface to an Analog Quadrature
Modulator (AQM) . . . . . . . . . . . . . . . . . . . . . . 34
10.13.3 AC interface to an Analog Quadrature
Modulator (AQM) . . . . . . . . . . . . . . . . . . . . . . 36
10.13.4 Phase correction . . . . . . . . . . . . . . . . . . . . . . 37
10.14 Power and grounding. . . . . . . . . . . . . . . . . . . 37
10.15 Configuration interface. . . . . . . . . . . . . . . . . . 37
10.15.1 Register description . . . . . . . . . . . . . . . . . . . . 37
10.15.2 Detailed descriptions of registers . . . . . . . . . . 37
10.15.2.1 Page 0 allocation map description . . . . . . . . . 38
10.15.2.2 Page 0 bit definition detailed description . . . . 40
10.15.2.3 Page 1 allocation map description . . . . . . . . . 46
10.15.2.4 Page 1 bit definition detailed description . . . . 47
10.15.2.5 Page 2 allocation map description . . . . . . . . . 51
10.15.2.6 Page 2 bit definition detailed description . . . . 52
10.15.2.7 Page 4 allocation map description . . . . . . . . . 56
10.15.2.8 Page 4 bit definition detailed description . . . . 58
10.15.2.9 Page 5 allocation map description . . . . . . . . . 68
10.15.2.10 Page 5 bit definition detailed description . . . 70
10.15.2.11 Page 6 allocation map description . . . . . . . . 77
10.15.2.12 Page 6 bit definition detailed description . . . 79
10.15.2.13 Page 7 allocation map description . . . . . . . . 83
10.15.2.14 Page 7 bit definition detailed description . . . 85
11
Package outline. . . . . . . . . . . . . . . . . . . . . . . . 89
12
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 90
13
Revision history . . . . . . . . . . . . . . . . . . . . . . . 91
14
Legal information . . . . . . . . . . . . . . . . . . . . . . 92
14.1
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 92
14.2
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
14.3
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 92
14.4
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 93
15
Contact information . . . . . . . . . . . . . . . . . . . . 93
16
Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
17
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2010.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [e-mail]
Date of release: 6 December 2010
Document identifier: DAC1208D750