DAC1208D750 Datasheet, PDF (69/98 Pages) NXP Semiconductors – Dual 12-bit DAC; up to 750 Msps; 2×, 4× or 8× interpolating with JESD204A interface

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Table 108. Page 5 register allocation map …continued
Address Register name R/W Bit definition
Default^[1]
b7
b6
b5
b4
b3
b2
b1
b0
Bin
Hex
17 11h FLAG_CNT_ R
MSB_LN0
FLAG_CNT_LN0[15:8]
uuuuuuuu uuh
18 12h FLAG_CNT_LSB R
_LN1
FLAG_CNT_LN1[7:0]
uuuuuuuu uuh
19 13h FLAG_CNT_ R
MSB_LN1
FLAG_CNT_LN1[15:8]
uuuuuuuu uuh
20 14h FLAG_CNT_LSB R
_LN2
FLAG_CNT_LN2[7:0]
uuuuuuuu uuh
21 15h FLAG_CNT_ R
MSB_LN2
FLAG_CNT_LN2[15:8]
uuuuuuuu uuh
22 16h FLAG_CNT_LSB R
_LN3
FLAG_CNT_LN3[7:0]
uuuuuuuu uuh
23 17h FLAG_CNT_ R
MSB_LN3
FLAG_CNT_LN3[15:8]
uuuuuuuu uuh
24 18h BER_LEVEL_ R/W
LSB
BER_LEVEL[7:0]
00000000 00h
25 19h BER_LEVEL_ R/W
MSB
BER_LEVEL[15:8]
00000000 00h
26 1Ah INTR_ENA
R/W INTR_
ENA_
NIT
INTR_ INTR_ENA_ INTR_ENA_ INTR_ENA_ INTR_ENA_ INTR_ENA_ INTR_ENA_ 00000000 00h
ENA_
KOUT
KOUT_
K28_7
K28_5
K28_3
MISC
DISP
UNEXP
27 1Bh CNTRL_
R/W
FLAGCNT_LN01
RST_
CFC_
LN1
SEL_CFC_LN1[2:0]
RST_CFC_
LN0
SEL_CFC_LN0[2:0]
01010101 55h
28 1Ch CNTRL_
R/W RST_
FLAGCNT_LN23
CFC_LN3
SEL_CFC_LN3[2:0]
RST_CFC_
LN2
SEL_CFC_LN2[2:0]
01010101 55h
29 1Dh MON_FLAGS_
RESET
R/W RST_NIT RST_ RST_KOUT RST_KOUT RST_K28_ RST_K28_ RST_K28_ RST_K28_ 00000000 00h
_ERR- DISP_ _FLAGS _UNEXPEC LN3_FLAGS LN2_FLAGS LN1_FLAGS LN0_FLAGS
FLAGS ERR_
TED_FLAGS
FLAGS
30 1Eh DBG_CNTRL
R/W BER_ INTR_
MODE CLEAR
INTR_MODE[2:0]
-
-
-
00000000 00h
31 1Fh PAGE_
R/W
-
-
-
-
-
ADDRESS
PAGE[2:0]
00000000 00h
[1] u = undefined at power-up or after reset.