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DAC1208D750 Datasheet, PDF (1/98 Pages) NXP Semiconductors – Dual 12-bit DAC; up to 750 Msps; 2×, 4× or 8× interpolating with JESD204A interface | |||
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DAC1208D750
Dual 12-bit DAC; up to 750 Msps; 2Ã, 4Ã or 8Ã interpolating
with JESD204A interface
Rev. 2 â 6 December 2010
Product data sheet
1. General description
The DAC1208D750 is a high-speed 12-bit dual channel Digital-to-Analog Converter
(DAC) with selectable 2Ã, 4Ã or 8Ã interpolating filters optimized for multi-carrier WCDMA
transmitters.
Because of its digital on-chip modulation, the DAC1208D750 allows the complex pattern
provided through lane 0, lane 1, lane 2 and lane 3, to be converted up from baseband to
IF. The mixing frequency is adjusted via a Serial Peripheral Interface (SPI) with a 32-bit
Numerically Controlled Oscillator (NCO) and the phase is controlled by a 16-bit register.
The DAC1208D750 also includes a 2Ã, 4Ã or 8Ã clock multiplier which provides the
appropriate internal clocks and an internal regulation to adjust the output full-scale
current.
The input data format is serial according to JESD204A specification. This new interface
has numerous advantages over the traditional parallel one: easy PCB layout, lower
radiated noise, lower pin count, self-synchronous link, skew compensation. The maximum
number of lanes of the DAC1208D750 is 4 and its maximum serial data rate is
3.125 Gbps.
The Multiple Device Synchronization (MDS) guarantees a maximum skew of one output
clock period between several DAC devices. MDS incorporates modes: Master/slave and
All slave mode.
2. Features and benefits
 Dual 12-bit resolution
 750 Msps maximum update rate
 Selectable 2Ã, 4à or 8à interpolation
filters
 Input data rate up to 312.5 Msps
 Very low noise cap free integrated PLL
 32-bit programmable NCO frequency
 Four JESD204A serial input lanes
 1.8 V and 3.3 V power supplies
 LVDS compatible clock inputs
 IMD3: 80 dBc; fs = 737.28 Msps;
fo = 140 MHz
 ACPR: 71 dBc; 2 carriers WCDMA;
fs = 737.28 Msps; fo = 153.6 MHz
 Typical 1.27 W power dissipation at 4Ã
interpolation, PLL off and 740 Msps
 Power-down mode and Sleep modes
 Differential scalable output current from
1.6 mA to 22 mA
 On-chip 1.25 V reference
 External analog offset control
(10-bit auxiliary DACs)
 Internal digital offset control
 Inverse (sin x) / x function
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