DAC1208D750 Datasheet, PDF (42/98 Pages) NXP Semiconductors – Dual 12-bit DAC; up to 750 Msps; 2×, 4× or 8× interpolating with JESD204A interface

NXP Semiconductors
DAC1208D750
2×, 4× or 8× interpolating DAC with JESD204A
Table 24. FREQNCO_MSB register (address 06h) bit description
Bit
Symbol
Access Value Description
7 to 0 FREQ_NCO[31:24]
R/W
26h
most significant 8 bits for the NCO frequency setting
Table 25. PHINCO_LSB register (address 07h) bit description
Bit
Symbol
Access Value
7 to 0 PH_NCO[7:0]
R/W
00h
Description
lower 8 bits for the NCO phase setting
Table 26. PHINCO_MSB register (address 08h) bit description
Bit
Symbol
Access Value
7 to 0 PH_NCO[15:8]
R/W
00h
Description
most significant 8 bits for the NCO phase setting
Table 27. DAC_A_CFG_1 register (address 09h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access Value
7
DAC_A_PD
R/W
0
1
6
DAC_A_SLEEP
R/W
0
1
5 to 0 DAC_A_OFFSET[5:0]
R/W
00h
Description
DAC A power
on
off
DAC A Sleep mode
disabled
enabled
lower 6 bits for the DAC A offset
Table 28. DAC_A_CFG_2 register (address 0Ah) bit description
Bit
Symbol
Access Value
7 to 6 DAC_A_GAIN_COARSE[1:0]
R/W
1h
5 to 0 DAC_A_GAIN_FINE[5:0]
R/W
00h
Description
least significant 2 bits for the DAC A gain setting for
coarse adjustment
the 6 bits for the DAC A gain setting for fine
adjustment
Table 29. DAC_A_CFG_3 register (address 0Bh) bit description
Bit
Symbol
Access Value Description
7 to 6 DAC_A_GAIN_COARSE[3:2]
R/W
3h
most significant 2 bits for the DAC A gain setting for
coarse adjustment
5 to 0 DAC_A_OFFSET[11:6]
R/W
00h
most significant 6 bits for the DAC A offset
DAC1208D750
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 6 December 2010
© NXP B.V. 2010. All rights reserved.
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