DAC1208D750 Datasheet, PDF (47/98 Pages) NXP Semiconductors – Dual 12-bit DAC; up to 750 Msps; 2×, 4× or 8× interpolating with JESD204A interface

NXP Semiconductors
DAC1208D750
2×, 4× or 8× interpolating DAC with JESD204A
10.15.2.4 Page 1 bit definition detailed description
Please refer to Table 47 for a register overview and their default values. In the following
tables, all the values emphasized in bold are the default values.
Table 48. MDS_MAIN register (address 00h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access Value
7 to 6 MDS_EQCHECK[1:0]
R/W
00
01
10
11
5
MDS_RUN
R/W
0
1
4
MDS_NCO
R/W
0
1
3
MDS_SEL_LN23
R/W
0
1
2
MDS_32T_ENA
1
MDS_MASTER
0
MDS_ENA
R/W
0
1
R/W
0
1
R/W
0
1
Description
lock mode
lock when (early = 1 and late = 1)
lock when (early = 1 and late = 1 and equal = 1)
lock when equal = 1
force_lock (equal-check = 1)
evaluation restart
no action
transition from 0 to 1 restarts evaluation_counter
NCO synchronization
no action
NCO synchronization enabled
synchronization reference
use lane 1 enable as reference for
synchronization
use lane 2/lane 3 enable as reference for
synchronization
maximum delay
maximum coarse delay is 16T_dclk
maximum coarse delay is 32T_dclk
MDS mode
slave mode
master mode
MDS function
disable MDS function
enable MDS function
Table 49. MDS_WIN_PERIOD_A register (address 01h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access Value Description
7 to 0 MDS_WIN_PERIOD_A[7:0]
R/W
80h
determines MDS window LOW-time
Table 50. MDS_WIN_PERIOD_B register (address 02h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access Value Description
7 to 0 MDS_WIN_PERIOD_B[7:0]
R/W
40h
determines MDS window HIGH-time
DAC1208D750
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 6 December 2010
© NXP B.V. 2010. All rights reserved.
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