TDA8920C Datasheet, PDF (6/40 Pages) NXP Semiconductors – 2 X110 W class-D power amplifier

NXP Semiconductors
TDA8920C
2 × 110 W class-D power amplifier
The TDA8920C single-chip class-D amplifier has built-in high-power switches, drivers,
timing and handshaking between the power switches and some control logic. In addition,
to secure maximum system robustness, an advanced protection strategy is implemented
for voltage, temperature and maximum current.
Both of the TDA8920C audio channels contain a PWM modulator, an analog feedback
loop and a differential input stage. The TDA8920C also contains circuits common to both
channels such as the oscillator, all reference sources, the mode interface and a digital
timing manager.
The two independent amplifier channels have high output power, high efficiency, low
distortion and low quiescent current. The amplifier channels can be connected in the
following configurations:
• Mono Bridge-Tied Load (BTL) amplifier
• Stereo Single-Ended (SE) amplifiers
The amplifier system can be switched to one of three operating modes using pin MODE:
• Standby mode: with a very low supply current
• Mute mode: the amplifiers are operational but the audio signal at the output is
suppressed by disabling the voltage-to-current (VI) converter input stages
• Operating mode: the amplifiers are fully operational with the output signal
To ensure pop noise-free start-up, the DC output offset voltage is applied gradually to the
output at a level between Mute mode and Operating mode levels. The bias-current setting
of the VI-converters is related to the voltage on pin MODE. In Mute mode the bias-current
setting of the VI-converters is zero (VI-converters are disabled). In Operating mode the
bias current is at maximum. The time-constant required to apply the DC output offset
voltage gradually between Mute and Operating mode levels can be generated using an
RC network on pin MODE. An example of a switching circuit for driving pin MODE is
illustrated in Figure 4. If the capacitor C is left out of the application the voltage on pin
MODE is applied with a much smaller time-constant, which may result in audible pop
noises during start-up (depending on the DC output offset voltage and loudspeaker used).
+5 V
standby/
mute
R
R
mute/on
Fig 4. Example of mode selection circuit
MODE pin
C
SGND
001aab172
TDA8920C_1
Preliminary data sheet
Rev. 01 — 29 September 2008
© NXP B.V. 2008. All rights reserved.
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