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| PHU78NQ03LT Datasheet, PDF (6/12 Pages) NXP Semiconductors – N-channel TrenchMOSTM logic level FET | |||
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NXP Semiconductors
PHU78NQ03LT
N-channel TrenchMOS logic level FET
Table 6. Characteristics â¦continued
Symbol Parameter
Conditions
td(on)
turn-on delay time
tr
rise time
td(off)
turn-off delay time
tf
fall time
Source-drain diode
VDS = 12 V; RL = 0.5 â¦; VGS = 5 V;
RG(ext) = 5.6 â¦; Tj = 25 °C
VSD
source-drain voltage IS = 25 A; VGS = 0 V; Tj = 25 °C;
see Figure 12
trr
reverse recovery time IS = 20 A; dIS/dt = -100 A/µs; VGS = 0 V;
Qr
recovered charge
VDS = 25 V; Tj = 25 °C
2.5
VGS(th)
(V)
2
1.5
1
max
typ
min
03aa33
0.5
0
-60
0
60
120
180
Tj (°C)
10-1
ID
(A)
10-2
10-3
10-4
10-5
10-6
0
Min Typ Max Unit
-
13
-
ns
-
46
-
ns
-
20
-
ns
-
15
-
ns
-
0.78 1.2 V
-
35
-
ns
-
20
-
nC
03aa36
min
typ
max
1
2
3
VGS (V)
Fig 5. Gate-source threshold voltage as a function of Fig 6. Sub-threshold drain current as a function of
junction temperature
gate-source voltage
PHU78NQ03LT_6
Product data sheet
Rev. 06 â 15 June 2009
© NXP B.V. 2009. All rights reserved.
6 of 12
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