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PHU78NQ03LT Datasheet, PDF (5/12 Pages) NXP Semiconductors – N-channel TrenchMOSTM logic level FET
NXP Semiconductors
PHU78NQ03LT
N-channel TrenchMOS logic level FET
6. Characteristics
Table 6. Characteristics
Symbol Parameter
Static characteristics
Conditions
V(BR)DSS
VGS(th)
drain-source
breakdown voltage
gate-source threshold
voltage
ID = 250 µA; VGS = 0 V; Tj = -55 °C
ID = 250 µA; VGS = 0 V; Tj = 25 °C
ID = 1 mA; VDS = VGS; Tj = -55 °C;
see Figure 5; see Figure 6
ID = 1 mA; VDS = VGS; Tj = 175 °C;
see Figure 5; see Figure 6
IDSS
IGSS
RDSon
drain leakage current
gate leakage current
drain-source on-state
resistance
ID = 1 mA; VDS = VGS; Tj = 25 °C;
see Figure 5; see Figure 6
VDS = 25 V; VGS = 0 V; Tj = 25 °C
VDS = 25 V; VGS = 0 V; Tj = 175 °C
VGS = 15 V; VDS = 0 V; Tj = 25 °C
VGS = -15 V; VDS = 0 V; Tj = 25 °C
VGS = 10 V; ID = 25 A; Tj = 25 °C;
see Figure 7; see Figure 8
VGS = 5 V; ID = 25 A; Tj = 175 °C;
see Figure 7; see Figure 8
VGS = 5 V; ID = 25 A; Tj = 25 °C;
see Figure 7; see Figure 8
RG
internal gate resistance f = 1 MHz; Tj = 25 °C
(AC)
Dynamic characteristics
QG(tot)
total gate charge
ID = 0 A; VDS = 0 V; VGS = 4.5 V;
Tj = 25 °C
ID = 25 A; VDS = 12 V; VGS = 4.5 V;
Tj = 25 °C; see Figure 9; see Figure 10
QGS
QGS1
gate-source charge
pre-threshold
gate-source charge
ID = 25 A; VDS = 12 V; VGS = 4.5 V;
Tj = 25 °C; see Figure 10; see Figure 10
QGS2
QGD
VGS(pl)
Ciss
post-threshold
gate-source charge
gate-drain charge
gate-source plateau
voltage
input capacitance
ID = 25 A; VDS = 12 V; Tj = 25 °C;
see Figure 9; see Figure 10
VDS = 12 V; VGS = 0 V; f = 1 MHz;
Tj = 25 °C; see Figure 11
Coss
output capacitance
Crss
reverse transfer
capacitance
Min Typ Max Unit
22
-
25
-
-
-
-
V
-
V
2.2 V
0.5 -
-
V
1
1.5 2
V
-
-
1
µA
-
-
500 µA
-
10
100 nA
-
10
100 nA
-
7.65 9
mΩ
-
18.9 24.3 mΩ
-
10.5 13.5 mΩ
-
1
-
Ω
-
8.6 -
nC
-
11
-
nC
-
3.6 -
nC
-
1.8 -
nC
-
1.8 -
nC
-
4
-
nC
-
3
-
V
-
970 -
pF
-
1460 -
pF
-
415 -
pF
-
170 -
pF
PHU78NQ03LT_6
Product data sheet
Rev. 06 — 15 June 2009
© NXP B.V. 2009. All rights reserved.
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