PHT4NQ10LT-135 Datasheet, PDF (6/13 Pages) NXP Semiconductors – N-channel TrenchMOS logic level FET

NXP Semiconductors
PHT4NQ10LT
N-channel TrenchMOS logic level FET
10^-1
I_D
(A)
10^-2
10^-3
10^-4
03aa36
min
typ
max
2.5
V_GS(th)
(V)
2
1.5
1
max
typ
min
03aa33
10^-5
0.5
10^-6
0
1
T_j = 25 °C; V_DS = 5 V
2
3
V_GS (V)
Fig 8. Sub-threshold drain current as a function of
gate-source voltage
1
R_{DSon 0.9}
(Ω)
0.8
0.7
2V 2.2V
2.4V
0.6
0.5
2.6V
0.4
0.3
0.2
0.1
0
012345
03ac86
T_j = 25°C
2.8V _3V
V_GS = 5V
6 7 8 9 10
I_D (A)
0
-60
0
60
120
180
T_j (°C)
Fig 9. Gate-source threshold voltage as a function of
junction temperature
3
03aa29
a
2
1
0
-60
0
60
120
180
T_j (°C)
Fig 10. Drain-source on-state resistance as a function Fig 11. Normalized drain-source on-state resistance
of drain current; typical values
factor as a function of junction temperature
PHT4NQ10LT
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 28 October 2011
© NXP B.V. 2011. All rights reserved.
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