PHT4NQ10LT-135 Datasheet, PDF (2/13 Pages) NXP Semiconductors – N-channel TrenchMOS logic level FET

NXP Semiconductors
PHT4NQ10LT
N-channel TrenchMOS logic level FET
3. Ordering information
Table 3. Ordering information
Type number
Package
Name
PHT4NQ10LT
SC-73
4. Marking
Description
plastic surface-mounted package with increased heatsink;
4 leads
Version
SOT223
Table 4. Marking codes
Type number
PHT4NQ10LT
5. Limiting values
Marking code
4NQ10L
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V_DS
V_DGR
V_GS
I_D
Parameter
drain-source voltage
drain-gate voltage
gate-source voltage
drain current
I_DM
peak drain current
Conditions
T_j ≥ 25 °C; T_j ≤ 150 °C
T_j ≥ 25 °C; T_j ≤ 150 °C; R_GS = 20 kΩ
T_sp = 100 °C; V_GS = 5 V
T_sp = 25 °C; V_GS = 5 V; see Figure 1;
see Figure 2
T_sp = 25 °C; pulsed; t_p ≤ 10 µs;
see Figure 1
P_tot
total power dissipation
T_stg
storage temperature
T_j
junction temperature
Source-drain diode
T_sp = 25 °C; see Figure 3
I_S
source current
I_SM
peak source current
Avalanche ruggedness
T_sp = 25 °C
T_sp = 25 °C; pulsed; t_p ≤ 10 µs
E_DS(AL)S
I_AS
non-repetitive drain-source
avalanche energy
non-repetitive avalanche
current
V_GS = 5 V; T_j = 25 °C; I_D = 3.5 A;
R_GS = 50 Ω; V_sup ≤ 15 V; unclamped;
t_p = 0.2 ms; see Figure 4
V_sup ≤ 15 V; V_GS = 5 V; T_j(init) = 25 °C;
R_GS = 50 Ω; unclamped; see Figure 4
Min Max Unit
-
100 V
-
100 V
-16 16 V
-
2.2 A
-
3.5 A
-
14 A
-
6.9 W
-65 150 °C
-65 150 °C
-
3.5 A
-
14 A
-
45 mJ
-
3.5 A
PHT4NQ10LT
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 28 October 2011
© NXP B.V. 2011. All rights reserved.
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