PHT4NQ10LT-135 Datasheet, PDF (3/13 Pages) NXP Semiconductors – N-channel TrenchMOS logic level FET

NXP Semiconductors
PHT4NQ10LT
N-channel TrenchMOS logic level FET
102
ID
RDSon = VDS/ ID
(A)
10
1
10-1 ^P
D.C.
δ = ^tp
T
10-2
tp
t
T
1
10
03ac48
tp = 10 µs
100 µs
1 ms
10 ms
100 ms
102 ^VDS 103
120
I_der
(%)
80
03aa25
40
0
0
50
100
150
200
T_sp (°C)
Fig 1. Safe operating area; continuous and peak drain Fig 2. Normalized continuous drain current as a
currents as a function of drain-source voltage
function of solder point temperature
120
P_der
(%)
80
03aa17
10
I_AS
(A)
03ac92
25°C
1
40
T_j prior to avalanche = 125°C
0
0
50
100
150
200
T_sp (°C)
Fig 3. Normalized total power dissipation as a
function of solder point temperature
10^−_110−2
10^−1
1 _{t p (ms)} 10
Unclamped inductive load; V_DD ≤ 15 V;
R_GS = 50 Ω; V_GS = 5 V; starting T_j = 25 °C and 125 °C.
Fig 4. Non-repetitive avalnche ruggednes current as a
function of pulse duration
PHT4NQ10LT
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 28 October 2011
© NXP B.V. 2011. All rights reserved.
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