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| PHT4NQ10LT-135 Datasheet, PDF (4/13 Pages) NXP Semiconductors – N-channel TrenchMOS logic level FET | |||
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NXP Semiconductors
PHT4NQ10LT
N-channel TrenchMOS logic level FET
6. Thermal characteristics
Table 6.
Symbol
Rth(j-sp)
Rth(j-a)
Thermal characteristics
Parameter
thermal resistance
from junction to solder
point
thermal resistance
from junction to
ambient
Conditions
mounted on a metal clad substrate
mounted on a printed-circuit board ;
minimum footprint
Min Typ Max Unit
-
-
18 K/W
-
-
150 K/W
102
Zth(j-sp)
(K/W)
10 d = 0.5
0.2
0.1
1 0.05
0.02
10-1
single pulse
10-2
10-5
10-4
10-3
10-2
03ac84
P
δ
=
tp
T
10-1
tp
t
T
1
tp(s) 10
Tsp = 25 °C
Fig 5. Transient thermal impedance from junction to solder point as a function of pulse duration
7. Characteristics
Table 7. Characteristics
Symbol
Parameter
Static characteristics
V(BR)DSS
drain-source
breakdown voltage
VGS(th)
gate-source threshold
voltage
IGSS
gate leakage current
Conditions
ID = 250 µA; VGS = 0 V; Tj = -55 °C
ID = 250 µA; VGS = 0 V; Tj = 25 °C
ID = 1 mA; VDS = VGS; Tj = 150 °C;
see Figure 9
ID = 1 mA; VDS = VGS; Tj = -55 °C;
see Figure 9
ID = 1 mA; VDS = VGS; Tj = 25 °C;
see Figure 9
VGS = -10 V; VDS = 0 V; Tj = 25 °C
VGS = 10 V; VDS = 0 V; Tj = 25 °C
Min Typ Max Unit
89 -
-
V
100 130 -
V
0.6 -
-
V
-
-
2.3 V
1
-
2
V
-
10
100 nA
-
10
100 nA
PHT4NQ10LT
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 â 28 October 2011
© NXP B.V. 2011. All rights reserved.
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