MK82FN256VLL15 Datasheet, PDF (51/94 Pages) NXP Semiconductors – High performance ARM

Peripheral operating requirements and behaviors
Table 39. Comparator and 6-bit DAC electrical specifications (continued)
Symbol
INL
DNL
Description
6-bit DAC integral non-linearity
6-bit DAC differential non-linearity
Min.
–0.5
–0.3
Typ.
—
—
Max.
0.5
0.3
Unit
LSB³
LSB
1. Typical hysteresis is measured with input voltage range limited to 0.6 to V_DD–0.6 V.
2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to
CMP_DACCR[DACEN], CMP_DACCR[VRSEL], CMP_DACCR[VOSEL], CMP_MUXCR[PSEL], and
CMP_MUXCR[MSEL]) and the comparator output settling to a stable level.
3. 1 LSB = V_reference/64
0.08
0.07
0.06
0.05
0.04
0.03
HYSTCTR
Setting
00
01
10
11
0.02
0.01
0
0.1 0.4 0.7
1
1.3 1.6 1.9 2.2 2.5 2.8 3.1
Vin level (V)
Figure 26. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0)
Kinetis K82 Sub-Family, Rev.1, 09/2015.
51
Freescale Semiconductor, Inc.