MK82FN256VLL15 Datasheet, PDF (49/94 Pages) NXP Semiconductors – High performance ARM

Peripheral operating requirements and behaviors
Table 38. ADC characteristics (V_REFH = V_DDA, V_REFL = V_SSA) (continued)
Symbol Description
E_FS Full-scale error
Conditions¹
• <12-bit modes
• 12-bit modes
• <12-bit modes
Min.
—
—
—
Typ.²
±0.5
–4
–1.4
Max.
–0.7 to
+0.5
–5.4
–1.8
Unit
Notes
LSB⁴ V_ADIN = V_DDA5
E_Q Quantization error
• ≤13-bit modes
—
—
±0.5
LSB⁴
ENOB Effective number of 16-bit differential mode
bits
• Avg = 32
6
12.8
14.5
—
bits
• Avg = 4
11.9
13.8
—
bits
16-bit single-ended mode
• Avg = 32
• Avg = 4
12.2
13.9
—
11.4
13.1
bits
—
bits
THD Total harmonic
distortion
16-bit differential mode
• Avg = 32
dB
7
—
-94
—
dB
16-bit single-ended mode
• Avg = 32
—
-85
—
SFDR Spurious free
dynamic range
16-bit differential mode
• Avg = 32
82
95
—
dB
7
—
dB
16-bit single-ended mode
78
90
• Avg = 32
E_IL Input leakage error
Temp sensor slope Across the full temperature
range of the device
V_TEMP25 Temp sensor voltage 25 °C
I_In × R_AS
1.55
1.62
1.69
706
716
726
mV
mV/°C
I_In = leakage
current
(refer to the
MCU's voltage
and current
operating
ratings)
8
mV
8
1. All accuracy numbers assume the ADC is calibrated with V_REFH = V_DDA
2. Typical values assume V_DDA = 3.0 V, Temp = 25 °C, f_ADCK = 2.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low
power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with
1 MHz ADC conversion clock speed.
4. 1 LSB = (V_REFH - V_REFL)/2^N
5. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11)
6. Input data is 100 Hz sine wave. ADC conversion clock < 12 MHz.
7. Input data is 1 kHz sine wave. ADC conversion clock < 12 MHz.
Kinetis K82 Sub-Family, Rev.1, 09/2015.
49
Freescale Semiconductor, Inc.