MK82FN256VLL15 Datasheet, PDF (25/94 Pages) NXP Semiconductors – High performance ARM

TRACECLK
Peripheral operating requirements and behaviors
Tr
Tf
Twh
Twl
Tcyc
Figure 8. TRACE_CLKOUT specifications
TRACE_CLKOUT
TRACE_D[3:0]
Ts
Th
Ts
Th
Figure 9. Trace data specifications
3.1.2 JTAG electricals
Table 14. JTAG limited voltage range electricals
Symbol
J1
Description
Operating voltage
TCLK frequency of operation
• Boundary Scan
• JTAG and CJTAG
• Serial Wire Debug
Min.
2.7
0
0
0
Max.
3.6
10
25
50
J2
TCLK cycle period
J3
TCLK clock pulse width
• Boundary Scan
• JTAG and CJTAG
• Serial Wire Debug
1/J1
—
50
—
20
—
10
—
J4
TCLK rise and fall times
J5
Boundary scan input data setup time to TCLK rise
J6
Boundary scan input data hold time after TCLK rise
J7
TCLK low to boundary scan output data valid
J8
TCLK low to boundary scan output high-Z
J9
TMS, TDI input data setup time to TCLK rise
J10
TMS, TDI input data hold time after TCLK rise
—
3
20
—
2.0
—
—
28
—
25
8
—
1
—
Table continues on the next page...
Unit
V
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Kinetis K82 Sub-Family, Rev.1, 09/2015.
25
Freescale Semiconductor, Inc.