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| PSMN5R5-60YS Datasheet, PDF (3/15 Pages) NXP Semiconductors – N-channel LFPAK 60 V, 5.2 mΩ standard level FET | |||
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NXP Semiconductors
PSMN5R5-60YS
N-channel LFPAK 60 V, 5.2 m⦠standard level FET
4. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
VDS
drain-source voltage Tj ⥠25 °C; Tj ⤠175 °C
VDGR
drain-gate voltage
Tj ⥠25 °C; Tj ⤠175 °C; RGS = 20 kâ¦
VGS
gate-source voltage
ID
drain current
Tmb = 100 °C; see Figure 1
Tmb = 25 °C; see Figure 1
[1]
IDM
peak drain current
tp ⤠10 µs; pulsed; Tmb = 25 °C; see Figure 3
Ptot
total power dissipation Tmb = 25 °C; see Figure 2
Tstg
storage temperature
Tj
junction temperature
Tsld(M)
peak soldering
temperature
Source-drain diode
IS
source current
Tmb = 25 °C;
[1]
ISM
peak source current tp ⤠10 µs; pulsed; Tmb = 25 °C
Avalanche ruggedness
EDS(AL)S
non-repetitive
VGS = 10 V; Tj(init) = 25 °C; ID = 100 A; Vsup ⤠60 V;
drain-source avalanche RGS = 50 â¦; unclamped
energy
[1] Continuous current is limited by package.
Min Max Unit
-
60
V
-
60
V
-20 20
V
-
74
A
-
100 A
-
418 A
-
130 W
-55 175 °C
-55 175 °C
-
260 °C
-
100 A
-
418 A
-
170 mJ
120
ID
(A)
100
(1)
80
60
40
20
0
0
50
003aad807
100
150
200
Tmb (°C)
120
Pder
(%)
80
03aa16
40
0
0
50
100
150
200
Tmb (°C)
Fig 1. Continuous drain current as a function of
mounting base temperature
Fig 2. Normalized total power dissipation as a
function of mounting base temperature
PSMN5R5-60YS_2
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 02 â 24 December 2009
© NXP B.V. 2009. All rights reserved.
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