TDA8595 Datasheet, PDF (29/50 Pages) NXP Semiconductors – I2C-bus controlled 4 ´ 45 W power amplifier

NXP Semiconductors
TDA8595
I²C-bus controlled 4 × 45 W power amplifier
Table 17. Characteristics …continued
Refer to test circuit (see Figure 30) at V_P = V_P1 = V_P2 = 14.4 V; R_L = 4 Ω; f = 1 kHz; R_S = 0 Ω; normal mode; unless otherwise
specified. Tested at T_amb = 25 °C; guaranteed for T_amb = −40 °C to +105 °C.
Symbol
Parameter
Conditions
Min
Typ
Max Unit
R_L(tol)
load resistance tolerance V_P ≤ 18 V
V_P ≤ 16 V
Mode select and second clip detection: pin STB
3.2
4
-
Ω
1.6
2
-
Ω
V_STB
voltage on pin STB
Standby mode selected
I²C-bus mode
-
-
1
V
legacy mode
-
-
1
V
mute selected
legacy mode
2.5
-
4.5
V
Operating mode selected
I²C-bus mode
legacy mode
low voltage on pin STB when
pulled down during clipping
2.5
-
6.5
-
[2]
V_P
V
V_P
V
I_STB = 150 µA
I_STB = 500 µA
I_STB
current on pin STB
V_STB from 0 V to 8.5 V
clip detection not active;
I²C-bus mode
5.6
-
6.1
-
-
4
6.1
V
7.2
V
30
µA
legacy mode
-
10
70
µA
Start-up / shut-down / mute timing
t_wake
wake-up time
time after wake-up via STB pin
-
before first I²C-bus transmission
is recognized; see Figure 4
300
500
µs
I_LO(SVR)
output leakage current on
pin SVR
-
-
10
µA
t_{d(mute_off)}
mute off delay time
10 % of output signal; I_LO = 0 µA ^[3]
I²C-bus mode;
295
465
795
ms
with I_LO = 10 µA → +15 ms;
no DC load (IB1[D1] = 0);
low pop disabled (IB2[D3] = 1);
see Figure 4
I²C-bus mode;
with I_LO = 10 µA → +20 ms;
DC load active (IB1[D1] = 1);
low pop disabled (IB2[D3] = 1);
see Figure 5
500
640
940
ms
I²C-bus mode;
with I_LO = 10 µA → +20 ms;
DC load active (IB1[D1] = 1);
low pop enabled (IB2[D3] = 0);
see Figure 6
640
830
1190 ms
legacy mode;
with I_LO = 10 µA → +20 ms;
V_STB = 7 V; R_ADSEL = 0 Ω;
see Figure 7
430
650
1030 ms
TDA8595_2
Product data sheet
Rev. 02 — 21 November 2007
© NXP B.V. 2007. All rights reserved.
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