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| 74HC193 Datasheet, PDF (19/30 Pages) NXP Semiconductors – Presettable synchronous 4-bit binary up/down counter | |||
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NXP Semiconductors
74HC193; 74HCT193
Presettable synchronous 4-bit binary up/down counter
VI
Dn input
VM
GND
VI
PL input
GND
VI
CPU, CPD
input
GND
VOH
Qn output
VOL
VM
tW
t PLH
VM
t rec
VM
t PHL
001aag415
Measurement points are given in Table 10.
tPLH and tPHL are the same as tpd.
Logic levels VOL and VOH are typical output voltage levels that occur with the output load.
Fig 11. The parallel load input (PL) and data (Dn) to Qn output propagation delays and PL removal time to clock
input (CPU, CPD)
VI
MR input
GND
VI
CPU, CPD
input
GND
VOH
Qn output
VOL
VM
tW
t rec
VM
t PHL
90 %
VM
10 %
t THL
t TLH
001aag416
Measurement points are given in Table 10.
tPLH and tPHL are the same as tpd.
Logic levels VOL and VOH are typical output voltage levels that occur with the output load.
Fig 12. The master reset input (MR) pulse width, MR to Qn propagation delays, MR to CPU, CPD removal time and
output transition times
74HC_HCT193
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 â 24 June 2013
© NXP B.V. 2013. All rights reserved.
19 of 30
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