74HC193 Datasheet, PDF (18/30 Pages) NXP Semiconductors – Presettable synchronous 4-bit binary up/down counter

NXP Semiconductors
11. Waveforms
74HC193; 74HCT193
Presettable synchronous 4-bit binary up/down counter
V_I
CPU, CPD
input
GND
V_OH
Qn output
V_OL
1/ f_max
V_M
t_W
t _PHL
V_M
t _PLH
001aag413
Measurement points are given in Table 10.
t_PLH and t_PHL are the same as t_pd.
Logic levels V_OL and V_OH are typical output voltage levels that occur with the output load.
Fig 9. The clock (CPU, CPD) to output (Qn) propagation delays, the clock pulse width, and the maximum clock
pulse frequency
V_I
CPU, CPD
input
V_M
GND
t_PHL
t_PLH
V_OH
TCU, TCD
output
V_M
V_OL
001aag414
Measurement points are given in Table 10.
t_PLH and t_PHL are the same as t_pd.
Logic levels V_OL and V_OH are typical output voltage levels that occur with the output load.
Fig 10. The clock (CPU, CPD) to terminal count output (TCU, TCD) propagation delays
74HC_HCT193
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 24 June 2013
© NXP B.V. 2013. All rights reserved.
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