74HC193 Datasheet, PDF (17/30 Pages) NXP Semiconductors – Presettable synchronous 4-bit binary up/down counter

NXP Semiconductors
74HC193; 74HCT193
Presettable synchronous 4-bit binary up/down counter
Table 9.
Symbol
t_rec
t_su
t_h
f_max
C_PD
Dynamic characteristics type 74HCT193 …continued
Parameter
Conditions
25 C
Min Typ
recovery time
PL to CPU, CPD;
see Figure 11
V_CC = 4.5 V
MR to CPU, CPD;
see Figure 12
10
2
set-up time
V_CC = 4.5 V
Dn to PL; see
Figure 13; note:
CPU = CPD =
HIGH
10
0
hold time
V_CC = 4.5 V
Dn to PL; see
Figure 13
16
8
V_CC = 4.5 V
CPU to CPD,
CPD to CPU; see
Figure 15
0
6
maximum
frequency
V_CC = 4.5 V
CPU, CPD; see
Figure 9
16
7
V_CC = 4.5 V
20
43
power
V_I = GND to V_CC  ^[2] -
26
dissipation
1.5 V; V_CC = 5 V;
capacitance
f_i = 1 MHz
40 C to +85 C 40 C to +125 C Unit
Max
Min Max Min
Max
-
13
-
15
- ns
-
13
-
15
- ns
-
20
-
24
- ns
-
0
-
0
- ns
-
20
-
24
- ns
-
16
-
13
- MHz
-
-
-
-
- pF
[1] t_pd is the same as t_PHL and t_PLH.
[2] C_PD is used to determine the dynamic power dissipation (P_D in W):
P_D = C_PD  V_CC2  f_i  N + (C_L  V_CC2  f_o) where:
f_i = input frequency in MHz;
f_o = output frequency in MHz;
C_L = output load capacitance in pF;
V_CC = supply voltage in V;
N = number of inputs switching;
(C_L  V_CC2  f_o) = sum of outputs.
74HC_HCT193
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 24 June 2013
© NXP B.V. 2013. All rights reserved.
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