TDA8262HN Datasheet, PDF (16/30 Pages) NXP Semiconductors – Fully integrated satellite tuner

Philips Semiconductors
TDA8262HN
Fully integrated satellite tuner
11.10 Bit description I²C-bus read mode
Table 29: Power-on reset; bit POR
POR Action
0
Normal operation
1
This bit is set to logic 1 at the V_CC(DIG) power supply ramp-up. It is reset to logic 0 after
the first read of the IC.
When V_CC(DIG) falls below 2 V typical, this bit is set to logic 1. This is to prevent loss in
internal I²C-bus registers programming.
Table 30: Synthesizer lock indicator; bit LOCK
LOCK Action
0
synthesizer is not locked
1
synthesizer is locked
Table 31: Auto calibration up threshold control; bit ACUP
ACUP Action
0
LC VCO tuning voltage is lower than VTH (see Table 24)
1
LC VCO tuning voltage is higher than VTH (see Table 24)
Table 32: Auto calibration down threshold control; bit ACDN
ACDN Action
0
LC VCO tuning voltage is higher than VTL (see Table 25)
1
LC VCO tuning voltage is lower than VTL (see Table 25)
Table 33: Calibration defect detection; bit ERRORCAL
ERRORCAL Action
0
no defect detected
1
calibration unit control tries to go lower than the minimum or higher than the
maximum Dword ratio
Table 34: RF input level indicator; bits INLEVEL[1:0]
This register gives the RF input level in dBm
INLEVEL1 INLEVEL0 Decimal RF power (dBm) ^[1]
0
0
0
< −30
0
1
1
−30 to −20
1
0
2
−20 to −15
1
1
3
> −15
[1] Typical values at nominal process and room temperature. Values are valid only when LNA path is selected
(bit RFATT = 0).
9397 750 13194
Product data sheet
Table 35: Internal Dword register; bits DW[4:0]
This register gives the internal Dword value. This value could be the programmed D[4:0] value in
manual mode or the calculated value after LC VCO calibration in automatic mode.
DW[4:0]
Description
Binary value
The f_LO to f_VCO ratio is the same as shown in Table 11
Rev. 01 — 14 December 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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