TDA8262HN Datasheet, PDF (1/30 Pages) NXP Semiconductors – Fully integrated satellite tuner

TDA8262HN
Fully integrated satellite tuner
Rev. 01 — 14 December 2004
Product data sheet
1. General description
The direct conversion QPSK demodulator is the front-end receiver dedicated to digital TV
broadcasting, satisfying both DVB-S and DBS TV standards. The wide range oscillator
(from 950 MHz to 2175 MHz) covers the American, European and Asian satellite bands,
as well as the SMA-TV US standard.
The Zero-IF (ZIF) concept discards traditional IF filtering and intermediate conversion
techniques.
Gain-controlled amplifiers in the RF guarantee optimum signal level. The variable gain is
controlled by the signal returned from the Satellite Demodulator and Decoder (SDD) and
applied to pin AGC.
The integrated LNA allows the IC to be directly connected to the LNB output. The LNA can
be by-passed by an I²C-bus selectable attenuation, providing a 20 dB extra attenuation in
order to handle higher input signal levels of up to 0 dBm per channel.
An integrated loop-through realizes a copy of the input RF signal for another
downconverter. This feature offers a BOM reduction and simplifies the application for dual
channel demodulation like watch and record.
Connected at the RF input, an RMS level detector provides through I²C-bus read mode
the full band input signal level.
The LO quadrature outputs are derived from a high performance integrated LC oscillator.
Its frequency is: -^f---^L---^O-- = -^f---^X---^T---^A---^L- . Thanks to the low phase noise performance of the
N
R
integrated LC oscillator which controls the LO frequency, the synthesizer offers a good
performance for phase noise in the satellite band. The step size of the LO output
frequency is equal to the comparison frequency.
Control data is entered via the I²C-bus. The bus can be either 5.0 V or 3.3 V, allowing
compatibility with most of existing microcontrollers.
An 8-byte frame is required to address the device and to program the main divider ratio,
the reference divider ratio, the charge-pump current and the operating mode.
A flag is set when the loop is in-lock, readable during read operations, as well as the
Power-on reset flag and RF input level.
The device has four selectable I²C-bus addresses. Applying a specific voltage to pin AS
selects an address. This feature gives the possibility to use up to four TDA8262HN ICs in
the same system.