M36W0R6040T3 Datasheet, PDF (15/23 Pages) Numonyx B.V – 64-Mbit (4 Mbits ×16, multiple bank, burst) Flash memory and 16-Mbit (1 Mbit ×16) or 32-Mbit (2 Mbits x16) PSRAM MCP

M36P0R9070E0
Functional description
Table 2. Main operating modes⁽¹⁾
Operation
A0-
E_F
G_F W_F RP_F
DPD_F WAIT
(2)
(3)
L
E_P W_P G_P UB_P LB_P CR_P
A19
A18
A17
A20-
DQ0-
DQ7
DQ8-
DQ15
A22
Bus Read
Bus Write
V_IL V_IL V_IH V_IH de-a⁽⁴⁾
V_IL V_IH V_IL V_IH de-a⁽⁴⁾
V_IL(5)
V_IL(5)
Address Latch V_IL X V_IH V_IH de-a⁽⁴⁾
V_IL
Output Disable V_IL V_IH V_IH V_IH de-a⁽⁴⁾ Hi-Z X
Standby
V_IH X X V_IH de-a⁽⁴⁾ Hi-Z X
Reset
X X X V_IL de-a⁽⁴⁾ Hi-Z X
Deep Power-
Down
V_IH X X V_IH a⁽⁷⁾ Hi-Z X
PSRAM must be disabled
Any PSRAM mode is allowed
Data Output
Data Input
Data Output or
Hi-Z⁽⁶⁾
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Word Read
V_IL V_IL V_IL V_IL
Valid
Output Output
Valid Valid
Lower Byte
Read
V_IH V_IL V_IH V_IL V_IL
Valid
Output
Valid
High-Z
Upper Byte
Read
V_IL V_IL V_IH V_IL
Valid
High-Z
Output
Valid
Word Write
Lower Byte
Write
Upper Byte
Write
X V_IL V_IL V_IL
The Flash memory must
be disabled
Low- ^VIL
Z
V_IL ^{VIL X VIH VIL VIL}
X V_IL V_IH V_IL
Valid
Valid
Valid
Input Input
Valid Valid
Input
Valid
Invalid
Invalid
Input
Valid
Read CR (CR
Controlled
Method)
Program CR
(CR
Controlled)⁽⁹⁾
V_IH V_IL V_IL V_IL
00(RCR)1
0(BCR)X1
(DIDR)⁽⁸⁾
X
BCR/RCR/
DIDR Content
V_{IH 00(RCR) BCR/}
V_IH X X X
10(BCR) RCR
(8)
Data
High-Z
No Operation
X X X X V_IL X X X
Deep Power-
Down⁽¹⁰⁾
Any Flash memory mode
is allowed
Hi-Z
X V_IH X X
X
X
X
X
X
X
Standby
V_IH X X X X V_IL X X X
X
High-Z
High-Z
1. X = Don't care, de-a = de-asserted, a = asserted, CR = Configuration Register.
2. The DPD_F signal polarity depends on the value of the ECR14 bit.
3. In the Flash memory the WAIT signal polarity is configured using the Set Configuration Register command.
4. If ECR15 is set to '0', the Flash memory cannot enter the Deep Power-Down mode, even if DPD_F is asserted.
5. In the Flash memory L can be tied to V_IH if the valid address has been previously latched.
6. Depends on G_F.
7. ECR15 has to be set to ‘1’ for the Flash memory to enter Deep Power-Down.
8. A18 and A19 are used to select the BCR, RCR or DIDR registers.
9. BCR and RCR only.
10. Bit 4 of the Refresh Configuration Register must be set to ‘0’, bit 4 (BCR4) of the Bus Configuration Register must be set to
‘0’, and E has to be maintained High, V_IH, during Deep Power-Down mode.
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