M36W0R6040T3 Datasheet, PDF (11/23 Pages) Numonyx B.V – 64-Mbit (4 Mbits ×16, multiple bank, burst) Flash memory and 16-Mbit (1 Mbit ×16) or 32-Mbit (2 Mbits x16) PSRAM MCP

M36P0R9070E0
Signal descriptions
2.10
Flash Reset (RP_F)
The Reset input provides a hardware reset of the Flash memories. When Reset is at V_IL, the
memory is in Reset mode: the outputs are high impedance and the current consumption is
reduced to the Reset Supply Current I_DD2. Refer to the M58PRxxxJ datasheet, for the value
of I_DD2. After Reset all blocks are in the Locked state and the Configuration Register is
reset. When Reset is at V_IH, the device is in normal operation. Exiting Reset mode the
device enters Asynchronous Read mode, but a negative transition of Chip Enable or Latch
Enable is required to ensure valid data outputs.
The Reset pin can be interfaced with 3V logic without any additional circuitry. It can be tied
to V_RPH (refer to the M58PRxxxJ datasheet).
2.11
PSRAM Chip Enable input (E_P)
The Chip Enable input activates the PSRAM when driven Low (asserted). When deasserted
(V_IH), the device is disabled, and goes automatically in low-power Standby mode or Deep
Power-down mode.
2.12
PSRAM Write Enable (W_P)
Write Enable, W_P, controls the Bus Write operation of the PSRAM. When asserted (V_IL), the
device is in Write mode and Write operations can be performed either to the configuration
registers or to the memory array.
2.13
PSRAM Output Enable (G_P)
Output Enable, G_P, provides a high speed tri-state control, allowing fast read/write cycles to
be achieved with the common I/O data bus.
2.14
PSRAM Upper Byte Enable (UB_P)
The Upper Byte En-able, UB_P, gates the data on the Upper Byte Data Inputs/Outputs (DQ8-
DQ15) to or from the upper part of the selected address during a Write or Read operation.
2.15
2.16
PSRAM Lower Byte Enable (LB_P)
The Lower Byte Enable, LB_P, gates the data on the Lower Byte Data Inputs/Outputs (DQ0-
DQ7) to or from the lower part of the selected address during a Write or Read operation.
If both LB_P and UB_P are disabled (High) during an operation, the device will disable the data
bus from receiving or transmitting data. Although the device will seem to be deselected, it
remains in an active mode as long as E_P remains Low.
PSRAM Configuration Register Enable (CR_P)
When this signal is driven High, V_IH, Write operations load either the value of the Refresh
Configuration Register (RCR) or the Bus configuration register (BCR).
11/23