M36W0R6040T3 Datasheet, PDF (10/23 Pages) Numonyx B.V – 64-Mbit (4 Mbits ×16, multiple bank, burst) Flash memory and 16-Mbit (1 Mbit ×16) or 32-Mbit (2 Mbits x16) PSRAM MCP

Signal descriptions
M36P0R9070E0
2.5
Wait (WAIT)
WAIT is an output pin common to the Flash memory and PSRAM components. However the
WAIT signal does not behave in the same way for the PSRAM and the Flash memory.
For details of how it behaves, please refer to the M69KB128AB datasheet for the PSRAM
and to the M58PR512J datasheet for the Flash memory.
2.6
Flash Chip Enable input (E_F)
The Flash Chip Enable input activates the control logic, input buffers, decoders and sense
amplifiers of the Flash memory component selected. When Chip Enable is Low, V_IL, and
Reset is High, V_IH, the device is in active mode. When Chip Enable is at V_IH the
corresponding Flash memory are deselected, the outputs are high impedance and the
power consumption is reduced to the standby level.
It is not allowed to have E_F at V_IL and E_P at V_IL at the same time. Only one memory
component can be enabled at a time.
2.7
Flash Output Enable inputs (G_F)
The Output Enable pins control the data outputs during Flash memory Bus Read
operations.
2.8
Flash Write Enable (W_F)
The Write Enable controls the Bus Write operation of the Flash memory Command
Interface. The data and address inputs are latched on the rising edge of Chip Enable or
Write Enable whichever occurs first.
2.9
Flash Write Protect (WP_F)
Write Protect is an input that gives an additional hardware protection for each block. When
Write Protect is Low, V_IL, Lock-Down is enabled and the protection status of the Locked-
Down blocks cannot be changed. When Write Protect is at High, V_IH, Lock-Down is disabled
and the Locked-Down blocks can be locked or unlocked. (See the Lock Status Table in the
M58PR512J datasheet).
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