M36W0R6050T1 Datasheet, PDF (14/22 Pages) STMicroelectronics – 64 Mbit (4 Mb ×16, Multiple Bank, Burst) Flash memory and 32 Mbit (2 Mb ×16) PSRAM, multi-chip package

Functional description
M36W0R6050T1, M36W0R6050B1
Table 2. Main operating modes
Operation
E_F G_P W_P L_F
RP_F WAIT_F(4) E1_P E2_P G_P
W_P UB_P LB_P DQ15-DQ0
Flash Read
V_IL V_IL V_IH V_IL(2) V_IH
Flash Data
Out
Flash Write
Flash Address
Latch
V_IL V_IH V_IL V_IL(2) V_IH
V_IL X V_IH V_IL V_IH
PSRAM must be disabled
Flash Data In
Flash Data
Out or Hi-Z
(3)
Flash Output
Disable
Flash Standby
Flash Reset
PSRAM Read
PSRAM Write
V_IL V_IH V_IH X V_IH
V_IH X X
XXX
X V_IH
X V_IL
Hi-Z
Hi-Z
Flash Memory must be disabled
Output Disable
PSRAM Standby
PSRAM Deep
Power-Down
Any Flash mode is allowed.
Flash Hi-Z
Any PSRAM mode is allowed
Flash Hi-Z
Flash Hi-Z
V_IL
V_IH
V_IL
V_IH
V_IL
V_IL
PSRAM data
out
V_IL
V_IH
V_IH
V_IL
V_IL
V_IL
PSRAM data
in
V_IL V_IH V_IH V_IH X
V_IH V_IH X X X
X PSRAM Hi-Z
X PSRAM Hi-Z
X V_IL X X X X PSRAM Hi-Z
1. X = Don't care.
2. L_F can be tied to V_IH if the valid address has been previously latched.
3. Depends on G_F.
4. WAIT signal polarity is configured using the Set Configuration Register command. Refer to M58WR064HT/B datasheet for
details.
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