M36W0R6050T1 Datasheet, PDF(13/22 Page) STMicroelectronics – 64 Mbit (4 Mb ×16, Multiple Bank, Burst) Flash memory and 32 Mbit (2 Mb ×16) PSRAM, multi-chip package

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M36W0R6050T1 Datasheet, PDF (13/22 Pages) STMicroelectronics – 64 Mbit (4 Mb ×16, Multiple Bank, Burst) Flash memory and 32 Mbit (2 Mb ×16) PSRAM, multi-chip package

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M36W0R6050T1, M36W0R6050B1

Functional description

The Flash memory and PSRAM components have separate power supplies but share the

same grounds. They are distinguished by three Chip Enable inputs: EF for the Flash

memory and E1P and E2P for the PSRAM.

Recommended operating conditions do not allow more than one device to be active at a

time. The most common example is simultaneous read operations on the Flash memory and

the PSRAM which would result in a data bus contention. Therefore it is recommended to put

the other devices in the high impedance state when reading the selected device.

Figure 3. Functional block diagram

VDDF VPPF VDDQF

A21

A0-A20

RPF

WPF

64 Mbit

Flash

Memory

VDDP

WAITF

DQ0-DQ15

E1P

E2P

UBP

LBP

32 Mbit

PSRAM

VSS

AI12.36

13/22

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