M36W0R6050T1 Datasheet, PDF (10/22 Pages) STMicroelectronics – 64 Mbit (4 Mb ×16, Multiple Bank, Burst) Flash memory and 32 Mbit (2 Mb ×16) PSRAM, multi-chip package

Signal descriptions
M36W0R6050T1, M36W0R6050B1
2.6
Flash Write Protect (WP_F)
Write Protect is an input that gives an additional hardware protection for each block. When
Write Protect is Low, V_IL, Lock-Down is enabled and the protection status of the Locked-
Down blocks cannot be changed. When Write Protect is at High, V_IH, Lock-Down is disabled
and the Locked-Down blocks can be locked or unlocked. (Refer to Lock Status Table in
M58WR064HT/B datasheet).
2.7
Flash Reset (RP_F)
The Reset input provides a hardware reset of the memory. When Reset is at V_IL, the
memory is in Reset mode: the outputs are high impedance and the current consumption is
reduced to the Reset Supply Current I_DD2. Refer to the M58WR064HT/B datasheet, for the
value of I_DD2. After Reset all blocks are in the Locked state and the Configuration Register is
reset. When Reset is at V_IH, the device is in normal operation. Exiting Reset mode the
device enters Asynchronous Read mode, but a negative transition of Chip Enable or Latch
Enable is required to ensure valid data outputs.
The Reset pin can be interfaced with 3V logic without any additional circuitry. It can be tied
to V_RPH (refer to the M58WR064HT/B datasheet).
2.8
Flash Latch Enable (L_F)
Latch Enable latches the address bits on its rising edge. The address latch is transparent
when Latch Enable is Low, V_IL, and it is inhibited when Latch Enable is High, V_IH. Latch
Enable can be kept Low (also at board level) when the Latch Enable function is not required
or supported.
2.9
Flash Clock (K_F)
The Clock input synchronizes the Flash memory to the microcontroller during synchronous
read operations; the address is latched on a Clock edge (rising or falling, according to the
configuration settings) when Latch Enable is at V_IL. Clock is don't care during Asynchronous
Read and in write operations.
2.10
2.11
Flash Wait (WAIT_F)
WAIT is a Flash output signal used during Synchronous Read to indicate whether the data
on the output bus are valid. This output is high impedance when Flash Chip Enable is at V_IH
or Flash Reset is at V_IL. It can be configured to be active during the wait cycle or one clock
cycle in advance. The WAIT_F signal is not gated by Output Enable.
PSRAM Chip Enable (E1_P)
When asserted (Low), the Chip Enable, E1_P, activates the memory state machine, address
buffers and decoders, allowing Read and Write operations to be performed. When de-
asserted (High), all other pins are ignored, and the device is automatically put in Standby
mode.
10/22