NS32FX211 Datasheet, PDF(9/12 Page) National Semiconductor (TI)

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NS32FX211 Datasheet, PDF (9/12 Pages) National Semiconductor (TI) – Microprocessor Compatible Real Time C

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Functional Description (Continued)

Interrupt Programming

The interrupt timer generates interrupts at time intervals

which are programmed into the interrupt register A single

interrupt after delay or repeated interrupts may be pro-

grammed Table IIB lists the different time delays and the

data words that select them in the interrupt register

Once the interrupt register has been used to set up the

delay time and to select for single or repeat it takes no

further part in the workings of the interrupt system All activi-

ty by the processor then takes place in the control register

Initializing

1) Write 3 to the control register (AD0) Clock timing contin-

ues interrupt register selected and interrupt timing stopped

2) Write interrupt control word to address 15 The interrupt

IIB) for the time delay required and for single or repeated

interrupts

3) Write 0 or 2 to the control register Interrupt timing com-

mences Writing 0 selects the clock setting register onto the

data bus writing 2 leaves the interrupt register selected

Normal timekeeping remains unaffected

On Interrupt

Read the control register and test for Interrupt Flag (bit 0)

If the flag is cleared (logic 0) then the device is not the

source of the interrupt

If the flag is set (logic 1) then the clock did generate an

interrupt The flag is reset and the interrupt output is cleared

by the control register read that was used to test for inter-

rupt

Single Interrupt Mode

When appropriate write 0 or 2 to the control register to

restart the interrupt timer

Repeated Interrupt Mode

Timing continues synchronized with the control register

write which originally started interrupt timing No further in-

tervention is necessary from the processor to maintain tim-

ing

In either mode interrupt timing can be stopped by writing 1

into the control register (interrupt start stop set to 1) Timing

for the full delay period recommences when the interrupt

start stop bit is again loaded with 0 as normal

IMPORTANT NOTE Using the interrupt timer places a con-

straint on the maximum Read Strobe width which may be

applied to the clock Normally all registers may be read from

with a tRW down to DC (i e CS and RD held continuously

low) When the interrupt timer is active however the maxi-

mum read strobe width that can be applied to the control

This restriction is to allow the interrupt timer to properly re-

set when it times out Note that it only affects reading of the

control register all other addresses in the clock may be

accessed with DC read strobes regardless of the state of

the interrupt timer Writes to any address are unaffected

APPLICATION HINTS

Time Reading Using Interrupt

In systems such as point of sale terminals and data loggers

time reading is usually only required on a random demand

basis Using the data-changed flag as outlined in the section

on methods of operation is ideal for this type of system

Some systems however need to sense a change in real

time e g industrial timers process controllers TV VCR

clocks any system where real time is displayed

The interrupt timer on the NS32FX211 can generate inter-

rupts synchronously with the time registers changing using

software to provide the initial synchronization

In single interrupt mode the processor is responsible for ini-

tiating each timing cycle and the timed period is accurate to

g1 ms

In repeated interrupt mode the period from the initial proces-

sor start to the first timeout is also only accurate to g1 ms

The following interrupts maintain accurate delay periods rel-

ative to the first timeout Thus to utilize interrupt to control

time reading we will use repeated interrupt mode

In repeated mode the time period between interrupts is ex-

act which means that timeouts will always occur at the

same point relative to the internal clock setting pulses The

case for 0 1s interrupts is shown in Figure A-1 The same is

true for other delay periods only there will be more clock

setting pulses between each interrupt timeout If we set up

the interrupt timer so that interrupt always times out just

after the clock setting pulse occurs (Figure A-2) then there

is no need to test the data-changed flag as we know that

the time data has just changed and will not alter again for

another 100 ms

This can be achieved as outlined below

1) Follow steps 1 and 2 of the section on interrupt program-

ming In step 2 set up for repeated interrupt

2) Read control register AD0 This is a dummy read to reset

the data-changed flag

3) Read control register AD0 until data-changed flag is set

4) Write 0 or 2 to control register Interrupt timing com-

mences

Time Reading with Very Slow Read Cycles

If a system takes longer than 100 ms to complete reading of

all the necessary time registers (e g when CMOS proces-

sors are used) or where high level interpreted language rou-

tines are used then the data-changed flag will always be set

when tested and is of no value In this case the time regis-

ters themselves must be tested to ensure data accuracy

The technique below will detect both time changing be-

tween read strobes (i e between reading tens of minutes

and units of hours) and also time changing during read

which can produce invalid data

1) Read and store the value of the lowest order time register

required

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