NS32FX211 Datasheet, PDF (8/12 Pages) National Semiconductor (TI) – Microprocessor Compatible Real Time C

Functional Description (Continued)
TABLE III The Control Register Layout
Access (addr0)
Read From
Write To
DB3
Data-Changed Flag
Test
0 e Normal
1 e Test Mode
DB2
0
Clock Start Stop
0 e Clock Run
1 e Clock Stop
DB1
0
Interrupt Select
0 e Clock Setting Register
1 e Interrupt Register
DB0
Interrupt Flag
Interrupt Start Stop
0 e Interrupt Run
1 e Interrupt Stop
Interrupt timing may be stopped in either mode by writing a
logic 1 into the interrupt start stop bit The timer is reset and
can be restarted in the normal way giving a full time delay
period before the next interrupt
In general the control register is set up such that writing 0’s
into it will start anything that is stopped pull the clock out of
test mode and select the clock setting register onto the bus
In other words writing 0 will maintain normal clock operation
and restart interrupt timing etc
The read only portion of the control register has two status
outputs
Since the NS32FX211 keeps real time the time data chang-
es asynchronously with the processor and this may occur
while the processor is reading time data out of the clock
Some method of warning the processor when the time data
has changed must thus be included This is provided for by
the data-changed flag located in bit 3 of the control register
This flag is set by the clock setting pulse which also clocks
the time registers Testing this bit can tell the processor
whether or not the time has changed The flag is cleared by
a read of the control register but not by any write operations
No other register read has any effect on the state of the
data-changed flag
Data bit 0 is the interrupt flag This flag is set whenever the
interrupt timer times out pulling the interrupt output low In a
polled interrupt routine the processor can test this flag to
determine if the NS32FX211 was the interrupting device
This interrupt flag and the interrupt output are both cleared
by a read of the control register
Both of the flags and the interrupt output are reset by the
trailing edge of the read strobe The flag information is held
latched during a control register read guaranteeing that sta-
ble status information will always be read out by the proces-
sor
Interrupt timeout is detected and stored internally if it occurs
during a read of the control register the interrupt output will
then go low only after the read has been completed
A clock setting pulse occurring during a control register read
will not affect the data-changed flag since time data read
out before or after the control read will not be affected by
the time change
Initialization
When it is first installed and power is applied the
NS32FX211 will need to be properly initialized The follow-
ing operation steps are recommended when the device is
set up (all numbers are decimal)
1) Disable interrupt on the processor to allow oscillator set-
ting Write 15₁₀ into the control register The clock and inter-
rupt start stop bits are set to 1 ensuring that the clock and
interrupt timers are both halted Test mode and the interrupt
register are selected
2) Write 0 to the interrupt register Ensure that there are no
interrupts programmed and that the oscillator will be gated
onto the interrupt output
3) Set oscillator frequency All timing has been halted and
the oscillator is buffered out onto the interrupt line
4) Write 5 to the control register The clock is now out of test
mode but is still halted The clock setting register is now
selected by the interrupt select bit
5) Write 0001 to all registers This ensures starting with a
valid BCD value in each register
6) Set 12 24 Hours Mode Write to the clock setting register
to select the hours counting mode required
7) Load Real-Time Registers All time registers (including
Leap Years and AM PM bit) may now be loaded in any
order Note that when writing to the clock setting register to
set up Leap Years and AM PM the Hours Mode bit must
not be altered from the value programmed in step 5
8) Write 0 to the control register This operation finishes the
clock initialization by starting the time The final control reg-
ister write should be synchronized with an external time
source
In general timekeeping should be halted before the time
data is altered in the clock The data can however be al-
tered at any time if so desired Such may be the case if the
user wishes to keep the clock corrected without having to
stop and restart it i e winter summer time changing can be
accomplished without halting the clock This can be done in
software by sensing the state of the data-changed flag and
only altering time data just after the time has rolled over
(data-changed flag set)
Reading the Time Registers
Using the data-changed flag technique supports microproc-
essors with block move facilities as all the necessary time
data may be read sequentially and then tested for validity as
shown below
1) Read the control register address 0 This is a dummy
read to reset the data-changed flag (DCF) prior to reading
the time registers
2) Read time registers All desired time registers are read
out in a block
3) Read the control register and test DCF If DCF is cleared
(logic 0) then no clock setting pulses have after occurred
since step 1 All time data is guaranteed good and time
reading is complete
If DCF is set (logic 1) then a time change has occurred
since step 1 and time data may not be consistent Repeat
steps 2 and 3 until DCF is clear The control read of step 3
will have reset DCF automatically repeating the step 1 ac-
tion
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