NS32FX211 Datasheet, PDF (3/12 Pages) National Semiconductor (TI) – Microprocessor Compatible Real Time C

AC Switching Characteristics
READ TIMING DATA FROM PERIPHERAL TO MICROPROCESSOR V_DD e 5V g5% C_L e 100 pF
Commercial Specification
Symbol
Parameter
T_A e 0 C to a75 C
Min
Typ
Max
t_AD
t_CSD
t_RD
t_RW
t_RA
Address Bus Valid to Data Valid
Chip Select On to Data Valid
Read Strobe On to Data Valid
Read Strobe Width (Note 3 Note 7)
Address Bus Hold Time from Trailing
Edge of Read Strobe
390
650
140
300
140
300
300
DC
0
t_CSH
Chip Select Hold Time from Trailing
0
Edge of Read Strobe
t_RH
Data Hold Time from Trailing
Edge of Read Strobe
70
160
t_HZ
Time from Trailing Edge of Read Strobe
250
Unitl O P Drivers are TRI-STATE
Units
ns
ns
ns
ns
ns
ns
ns
ns
WRITE TIMING DATA FROM MICROPROCESSOR TO PERIPHERAL V_DD e 5V g5%
Commercial Specification
Symbol
Parameter
T_A e 0 C to a70 C
Min
Typ
Max
Units
t_AW
Address Bus Valid to Write Strobe O
400
125
ns
(Note 4 Note 6)
t_CSW
Chip Select On to Write Strobe O
250
100
ns
t_DW
Data Bus Valid to Write Strobe O
400
220
ns
t_WW
Write Strobe Width (Note 6)
250
95
ns
t_WCS
Chip Select Hold Time Following
0
ns
Write Strobe O
t_WA
Address Bus Hold Time Following
0
ns
Write Strobe O
t_WD
Data Bus Hold Time Following
100
35
ns
Write Strobe O
t_AWS
Address Bus Valid before
70
20
ns
Start or Write Strobe
Note 3 Except for special case restriction with interrupts programmed max read strobe width of control register (ADDR 0) is 30 ms See section on Interrupt
Programming
Note 4 All timings measured to the trailing edge of write strobe (data latched by the trailing edge of WR)
Note 5 Input test waveform peak voltages are 2 4V and 0 4V Output signals are measured to their 2 4V and 0 4V levels
Note 6 Write stobe as used in the Write Timing Table is defined as the period when both chip select and write inputs are low ie WS e CS a WR Hence write
strobe commences when both signals are low and terminates when the first signal returns high
Note 7 Read strobe as used in the Read Timing Table is defined as the period when both chip select and read inputs are low ie RS e CS a RD
Note 8 Typical numbers are at V_CC e 5 0V and T_A e 25 C
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