NS32FX211 Datasheet, PDF (7/12 Pages) National Semiconductor (TI) – Microprocessor Compatible Real Time C

Functional Description (Continued)
TABLE IIA Clock Setting Register Layout
Function
Leap Year Counter
AM PM Indicator (12-Hour Mode)
12 24-Hour Select Bit
DB3
X
Data Bits Used
DB2
DB1
X
X
DB0
X
Comments
0 Indicates a Leap Year
0 e AM 1 e PM
0 in 24-Hour Mode
0 e 12-Hour Mode
1 e 24-Hour Mode
TABLE IIB Interrupt Control Register
Function
Comments
Control Word
DB3
DB2
DB1
No Interrupt
Interrupt Output Cleared
X
0
0
Start Stop Bit Set to 1
0 1 Second
01
0
0
0 5 Second
01
0
1
1 Second
01
0
1
5 Seconds
DB3 e 0 for Single Interrupt
01
1
0
DB3 e 1 for Repeated Interrupt
10 Seconds
01
1
0
30 Seconds
01
1
1
60 Seconds
01
1
1
Timing Accuracy Single Interrupt Mode (all time delays) g1 ms
Repeated Mode g1 ms on Initial Timeout Thereafter Synchronous with First Interrupt (i e timing errors do not
accumulate)
Access
RW
RW
RW
DB0
0
1
0
1
0
1
0
1
Control Register
There are three registers which control different operations
of the clock
a the clock setting register
b the interrupt register
c the control register
The clock setting and interrupt registers both reside at ad-
dress 15 access to one or the other being controlled by the
interrupt select bit data bit 1 of the control register
The clock setting register programs the timekeeping of the
clock The 12 24-hour mode select and the AM PM indica-
tor for 12-hour mode occupy bits 0 and 1 respectively Data
bits 2 and 3 set the leap year counter
The interrupt register controls the operation of the interrupt
timer selecting the required delay period and either single
or repeated interrupt
The control register is responsible for controlling the opera-
tions of the clock and supplying status information to the
processor It appears as two different registers one with
write only access and one with read only access
The write only register consists of a bank of four latches
which control the internal processes of the clock
The read only register contains two output data latches
which will supply status information for the processor Table
III shows the mapping of the various control latches and
status flags in the control register The control register is
located at address 0
The write only portion of the control register contains four
latches
A logic 1 written into the test bit puts the device into test
mode This allows setting of the oscillator frequency For
normal operation the test bit is loaded with logic 0
The clock start stop bit stops the timekeeping of the clock
and resets to 0 the tenths of seconds counter The time of
day may then be written into the various clock registers and
the clock restarted synchronously with an external time
source Timekeeping is maintained thereafter
A logic 1 written to the start stop bit halts clock timing Tim-
ing is restarted when the start stop bit is written with a logic
0
The interrupt select bit determines which of the two regis-
ters mapped onto address 15 will be accessed when this
address is selected
A logic 0 in the interrupt select bit makes the clock setting
register available to the processor A logic 1 selects the
interrupt register
The interrupt start stop bit controls the running of the inter-
rupt timer It is programmed in the same way as the clock
start stop bit logic 1 to halt the interrupt and reset the tim-
er logic 0 to start interrupt timing
When no interrupt is programmed (interrupt control register
set to 0) the interrupt start stop bit is automatically set to a
logic 1 When any new interrupt is subsequently pro-
grammed timing will not commence until the start stop bit
is loaded with 0
In the single interrupt mode interrupt timing stops when a
timeout occurs The processor restarts timing by writing log-
ic 0 into the start stop bit
In repeated interrupt mode the interrupt timer continues to
count with no intervention by the processor necessary
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