DS92LV2411 Datasheet, PDF (9/40 Pages) National Semiconductor (TI) – 5-50MHz 24-Bit Channel Link II Serializer and Deserializer

Pin Name
Pin #
I/O, Type Description
ID[x]
56
I, Analog I2C Serial Control Bus Device ID Address Select — Optional
Resistor to Ground and 10 kΩ pull-up to 1.8V rail. (See Table 10).
SCL
SDA
3
I, LVCMOS I2C Serial Control Bus Clock Input - Optional
SCL requires an external pull-up resistor to V_DDIO.
2
I/O,
I2C Serial Control Bus Data Input / Output - Optional
LVCMOS SDA requires an external pull-up resistor to V_DDIO.
Open Drain
BISTEN
44
I, LVCMOS BIST Enable Input — Optional
w/ pull-down BISTEN = 0, BIST is disabled (normal operation)
BISTEN = 1, BIST is enabled
RES
47
I, LVCMOS Reserved - tie LOW
w/ pull-down
NC
1, 15, 16,
30, 31, 45,
46, 60
Not Connected
Leave pin open (float)
Channel-Link II — CML Serial Interface
RIN+
49
I, CML True Input. The input must be AC Coupled with a 0.1 μF capacitor.
RIN-
50
I, CML Inverting Input. The input must be AC Coupled with a 0.1 μF capacitor.
CMF
51
I, Analog Common-Mode Filter
VCM center-tap is a virtual ground which may be ac-coupled to ground to increase receiver
common mode noise immunity. Recommended value is 4.7 μF or higher.
ROUT+
52
O, CML True Output — Receive Signal after the Equalizer
NC if not used or connect to test point for monitor. Requires I2C control to enable.
ROUT-
53
O, CML Inverting Output — Receive Signal after the Equalizer
NC if not used or connect to test point for monitor. Requires I2C control to enable.
Power and Ground
VDDL
29
Power Logic Power, 1.8 V ±5%
VDDIR
48
Power Input Power, 1.8 V ±5%
VDDR
43, 55
Power RX High Speed Logic Power, 1.8 V ±5%
VDDSC
4, 58
Power SSCG Power, 1.8 V ±5%
VDDPR
57
Power PLL Power, 1.8 V ±5%
VDDCMLO
54
Power RX High Speed Logic Power, 1.8 V ±5%
VDDIO
GND
13, 24, 38
DAP
Power
Ground
LVCMOS I/O Power, 1.8 V ±5% OR 3.3 V ±10% (V_DDIO)
DAP is the large metal contact at the bottom side, located at the center of the LLP package.
Connected to the ground plane (GND) with at least 9 vias.
NOTE: 1 = HIGH, 0 = LOW
The VDD (V_DDn and V_DDIO) supply ramp should be faster than 1.5 ms with a monotonic rise. If slower then 1.5 ms then a capacitor
on the PDB pin is needed to ensure PDB arrives after all the VDD have settled to the recommended operating voltage.
9
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