DS92LV2411 Datasheet, PDF (5/40 Pages) National Semiconductor (TI) – 5-50MHz 24-Bit Channel Link II Serializer and Deserializer

Pin Name
Pin #
I/O, Type Description
CONFIG
[1:0]
13, 12
I, LVCMOS 00: Control Signal Filter DISABLED
w/ pull-down 01: Control Signal Filter ENABLED
10: Reverse compatibility mode to interface with the DS90UR124 or DS99R124Q
11: Reverse compatibility mode to interface with the DS90C124
ID[x]
6
I, Analog I2C Serial Control Bus Device ID Address Select — Optional
Resistor to Ground and 10 kΩ pull-up to 1.8V rail. See Table 10.
SCL
SDA
BISTEN
8
I, LVCMOS I2C Serial Control Bus Clock Input - Optional
SCL requires an external pull-up resistor to V_DDIO.
9
I/O, LVCMOS I2C Serial Control Bus Data Input / Output - Optional
Open Drain SDA requires an external pull-up resistor V_DDIO.
31
I, LVCMOS BIST Mode — Optional
w/ pull-down BISTEN = 0, BIST is disabled (normal operation)
BISTEN = 1, BIST is enabled
RES[2:0]
18, 16, 15 I, LVCMOS Reserved - tie LOW
w/ pull-down
Channel-Link II — CML Serial Interface
DOUT+
20
O, CML Non–Inverting Output.
The output must be AC Coupled with a 0.1 µF capacitor.
DOUT-
19
O, CML Inverting Output.
The output must be AC Coupled with a 0.1 µF capacitor.
Power and Ground
VDDL
7
Power Logic Power, 1.8 V ±5%
VDDP
14
Power PLL Power, 1.8 V ±5%
VDDHS
17
Power TX High Speed Logic Power, 1.8 V ±5%
VDDTX
22
Power Output Driver Power, 1.8 V ±5%
VDDIO
30
Power LVCMOS I/O Power, 1.8 V ±5% OR 3.3 V ±10%
GND
DAP
Ground
DAP is the large metal contact at the bottom side, located at the center of the LLP
package. Connect to the ground plane (GND) with at least 9 vias.
NOTE: 1= HIGH, 0 L= LOW
The VDD (V_DDn and V_DDIO) supply ramp should be faster than 1.5 ms with a monotonic rise. If slower then 1.5 ms then a capacitor
on the PDB pin is needed to ensure PDB arrives after all the VDD have settled to the recommended operating voltage.
5
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